D flip-flop standard cell

VLSI and ASIC Technology
Standard Cell Library Design

open sauce gushes

Full Library Release ... January 12, 2008
Required software versions

Added on September 22, 2008:  Script that provides unique functions for 1-4 input cells.
Added on July 14, 2008:  Paper on achieving fastest Alliance synthesis results.
Added on January 12, 2008:  Release 8.5 of the standard cell libraries.
Updated on November 5, 2007:  A table giving a quick check of some standard cell library densities.
Updated on November 4, 2007:  Review of open source standard cell libraries.
Updated on October 28, 2007:  33 page paper about on-chip IR drop.
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Full library release: pharosc-8.5.tar.gz

This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design.

This material includes standard cell libraries, which are made available under the terms of the GNU Lesser General Public Licence. There are no restrictions on using these libraries in an integrated circuit, and they can be copied, modified and distributed under terms of your choice provided that the original copyright is prominently displayed (see section 6 of the licence).

Standard cell library information

There are five new open source standard cell libraries, the vsclib, wsclib, vxlib, vgalib and rgalib. They have been drawn with the Graal software from Alliance, part of an extensive open source software suite for designing integrated circuits with a standard cell design methodology.

The libraries have been characterised in a generic 0.13µm technology. The spice model comes from the University of California, Berkeley.

The layout has been drawn using MOSIS layer numbers and names and the pharosc rule set, and then scaled to what are slightly oversized 0.13µm rules which should be compatible with most foundries.

The vxlib is compatible with the sxlib created by the Alliance software authors. The vsclib is a completely new library design. The wsclib is derived from the vsclib. The rgalib and vgalib are small gate array type libraries.

The Alliance sxlib has also been characterised in 0.13µm using the same methodology and converted to the same 0.13µm layout rules. There is also an ssxlib which is the Alliance sxlib converted with a script from 1µm to 2µm layout and adjusted to obey DSM layout rules. The adjustments change the timing slightly.

The characterisation methodology creates a web data book, and this is on-line with the cells' layout and schematics.

Recent releases

In Release 8.1, the wsclib and ssxlib have been added. There are variants called stxlib, vtxlib, vtclib and wtclib which allow routing on the metal-1 level. See the examples directory in the release file for more details.

Release 8.2 has increased the size of the vsclib and wsclib, improving a number of the cell layouts and adding a D flip‑flop. Two small gate array libraries have also been added.

Release 8.3 has added a latch to the vsclib and wsclib, and expanded the examples directory. Each cell's fixed delay in the Alliance VBE file used for VHDL simulation has been set to the cell delay driving 25fF.

Release 8.4 has some small corrections and help files for working from a Linux Live CD.

Release 8.5 has much improved support for Magic including a single tech file, updated DRC files, completely revised extraction parameters and extraction flow which avoids the previous kludge, and improved colours for viewing the cells.

Library development flow

The library development flow uses Graal for the layout entry, and S2r to convert the layout to a CIF file. The CIF file is read into Magic which is used to extract a Spice deck and write CIF and GDS layout files. Magic has stronger features than S2r for converting layout drawings to CIF.

The extracted spice decks are simulated with Winspice3 using a 0.13µm BSIM3 model from the University of California, Berkeley. A comprehensive characterisation script is used, making it easy to add new cells.

The transistor schematics for the libraries have been drawn with Xcircuit, which uses Postscipt as its native file format.

The characterisation results are formatted with scripts into a Synopsys Liberty .LIB format and an Alliance VBE format. The Synopsys format is an industry standard, and the .LIB files use table lookup for accuracy which matches or exceeds that of commercially available libraries. The Alliance VBE format allows the library to be used with the Alliance P&R software, Ocp and Nero, and simulated with Asimut.
OCP for place and NERO for route need their source code modified and then recompiled to use these libraries. Compiled versions made under Ubuntu 7.04 on Intel hardware are included in the examples directory in the library release, and in

Help pages

Web pages offer help in downloading, viewing and characterising the cells. The Windows help is for native Windows and for booting a Windows computer from a Linux Live CD like Ubuntu 6.10 and 7.04. I don't use Windows much so I can't offer much help on its use with Alliance. Frankly it is not an operating system well suited to engineering work, more like a toy really, so a Linux Live CD is a good option for Windows users. The Linux help is for users who have Linux installed as their operating system.

The libraries were first released on September 25, 2003, with a number of revisions since then.

There is an extensive README.txt file to help in using the library. The text files on this site have all been created on a Linux system which uses <LF> for new lines. Windows uses <CR><LF>, and some Windows programs don't properly handle files using <LF> only. One of these is Notepad, the default viewer for TXT files. Wordpad allows these files to be viewed properly.

In addition to the standard cell libraries, there is a discussion of logical effort and how it has been used for sizing the vsclib and vxlib transistors. There is a paper on supply line IR drop (33 pages) and how to size the power supplies to avoid problems. The paper on choosing the cells in a standard cell library shows the benefits of adding cells to a library.

Full details of the revision history are in the revision.txt file.

Alliance synthesis paper
Synthesis paper summary

A paper which shows how to achieve the fastest netlists using the Alliance synthesis tools BOOM, BOOG and LOON. The sclib is used as an example, because it is an simple library and has some limitations which need fixing to get the best synthesis results. The paper introduces some scripts which make it easy to get the fastest netlist.
July 14, 2008

IR drop paper
IR drop paper summary

Read the paper on how to size integrated circuit power buses based on the core power consumption and desired on chip IR drop. This is an extensive discussion of the topic running to 33 pages, which you won't easily find described elsewhere.
Thoroughly revised on October 28, 2007

Synopsys Magma patent dispute paper

A 10 page paper which analyses the van Ginneken U.S. patent number 6,725,438 at the heart of the dispute between Synopsys and Magma. A 4-bit adder using an open source standard cell library is used as a real example to test the patent claims and measure them against prior art and a manual optimisation.
Old now, dating from August 2005

Choosing standard cell library cells

36 pages documenting a methodology for choosing which cells to include in a library.
November 2006

standard cell library info
view sxlib on-line data book
view ssxlib on-line data book
view vxlib on-line data book
view vsclib on-line data book
view wsclib on-line data book
view vgalib on-line data book
view rgalib on-line data book

Information and downloads for 7 standard cell libraries which have been designed to support The Art of Standard Cell Library Design. The January 12 release, 8.5, is a full release, now with 322 cells in the vsclib and wsclib. The cell layouts are provided in Graal, Magic, CIF and GDS formats.
See sxlib013.lib, ssxlib013.lib, vxlib013.lib, vsclib013.lib, wsclib013.lib, vgalib013.lib and rgalib013.lib for the latest Synopsys Liberty .LIB files.
The ssxlib is derived from the sxlib, but the rules have been changed to better support the requirements of deep submicron layout. When the layout is converted to a 0.13µm generic rule set, it looks a lot better and doesn't have the DRC violations of the sxlib.

Lambda layout rules
Generic 0.13µm layout rules

Overview of the pharosc lambda design rules together with those from MOSIS and Alliance.
Updated on August 4, 2007.

Survey of standard cell libraries

A brief survey of open source standard cell libraries which can be downloaded from the web. Updated on November 4, 2007.

choosing the cells in a standard cell library

Discussion and proposal on which cells to include in a small standard cell library. Links to three other papers on the subject. Updated on April 26, 2006.

Survey of IC layout software

A brief survey of software for IC polygon pushing layout which can be downloaded from the web, and other programs for which you must pay money. Updated on October 30, 2007.

Script to calculate unique functions

This bash script will print a list of the unique functions that are possible for cells with 1,2,3 or 4 inputs.


Interesting and Related Links:

WinSpice3 simulator

WinSpice3 is the Spice program used to characterise the libraries on this web site. It works in both Windows and Linux with codeweavers and wine. Free download, very cheap registration, powerful control statements, BSIM3 support and excellent documentation. You'll probably need it to run the Spice characterisation routines in the library download file.

Steve Golson's papers

Steve Golson has won many Best Paper awards at SNUG Conferences. His papers and some scripts are gathered on this page. The paper on wireloads from SNUG 1999 is particularly good.

reference book on logical effort

The book on Logical Effort by Ivan Sutherland, Bob Sproull and David Harris is strongly recommended. This web site has some supporting information. You can also read my discussion on logical effort.

Alliance CAD Tools
Wikipedia entry on standard cells
Open Source Fedora
Oceanstream LLC
Prof Jake Baker's homepage
Jonah Probell's homepage

Sites which are listing www.vlsitechnology.org and might contain other material of interest to you.


Search sites which list this site in the top three with the search keywords "asic standard cell". The duckduckgo service actually places this site first!

last update March 18, 2013
Graham Petley, +44-1539-722655 and
graham.petley at vlsitechnology dot org
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