Adder4 example with vsclib, vxlib and sxlib

The library release has tested the 3 libraries with a variant of the Alliance adder4 example. Two 4 bit numbers are summed to a 5 bit output. Timing and layout are generic 0.13µm. Various synthesis flows have been used, with the focus on fastest speed. For the preferred one, the best results are in the table on the right. Delay is driving a 50fF load and includes the RC product of a 1kΩ input driving resistance and the input capacitance. The layouts and schematics with critical path are shown below. Click on them to see the graphics better.

The sxlib is slower because it has no carry generator cells, which provide the best performance. It also has a very limited set of drive strengths. It has the best routability, but at the expense of higher input pin capacitances. The vsclib has shorter cells, and uses an 8λ metal pitch rather than the 10λ pitch used by the sxlib and vxlib, and this translates to smaller layout.

vsclib

vxlib

sxlib

vsclib critical path

vxlib critical path

sxlib critical path