| Paper by Nguyen and Sakurai |
The Choice of Cells to Include in a Standard Cell Library |
||||
| Paper by Masgonty, Cserveny, Arm, Pfister and Piguet | |||||
|
The question of which cells to include in a standard cell library is an important one. The best way to deliver a library is in staged releases. The first release is made quickly with a limited set of cells, but these need to be well chosen so that as much as possible of a technology's performance is available to the user. Further releases add new cells as they are designed, but there is no point in continuing to add cells which have no real impact on a circuit's speed, area or power. So the questions are:
Which cells should be included in a first library release? |
Paper by Nguyen and SakuraiPaper which concludes that a standard cell library with only 20 cells has the same performance as libraries with 400 cells. This assertion is tested with 31 benchmark designs. These designs are structural netlists that use simple primitives which are then re-targeted to three vendor libraries for the analysis. The least used cells are successively removed and the circuit performance measured. Starting with 400 cells, the authors found no significant loss in speed even with a library set of 20 cells. 17 of these cells are combinational logic with just 11 different functions being used. |
Paper by Masgonty et al.Paper which describes a library design exercise with the aim of including only the most useful cells in a library. The authors had already designed one library, the CSEL-LIB 4, and the speed of the new library, the CSEL-LIB 5 was compared to the previous one as new cells were added. The conclusion is that just 22 different logic function are needed, but with 92 different cells because each function is supplied with many different drive strengths. The paper doesn't say how many of these 22 functions are combinational and no cell list is given. |
|||
|
There seems to be only two papers covering this subject, and both of these conclude that a small library has essentially the same performance as a big one. Many other papers, while not discussing the issue of which cells to actually put into a library, claim that a rich library aids in meeting speed goals. A typical paper might analyse where performance was not being met in a design and conclude that it is because a few cells (eg. high drive adders) were missing from a library. There are even entire companies making a living by selling software that synthesises library functions to optimise timing for specific critical paths. The concept is that the only way to achieve the speed goals is to add more cells to the library, and this software allows the user to do this on the fly. |
Proposed List of Standard CellsThis proposal is for a small library of 51 combinational logic cells. The drive strength x2 corresponds to a maximum width single output P-transistor (28λ for the vsclib, 38λ for the vxlib for example). A 0.13µm process has a lambda of 0.055µm, so these would be widths of 1.485µm and 2.09µm. The first block of 17 cells corresponds more or less to the ones proposed by Nguyen and Sakurai, even though the nr3v0x1 would be explicitly excluded by Masgonty et al. The second column of cells are the next 17 that seem most useful, and the third column is the final 17 to complete the library. |
1st 17 |
2nd 17 |
3rd 17 |
|
| Last update January 3, 2004 |
|||||