dfnt1 standard cell family

 Rising clock edge D flip-flop
dfnt1 symbol
D-type flip-flop with single x2 drive strength non-inverted output clocked on the rising edge of pin cp. Clocked inverters are used on the input and feedback nodes, and a CMOS transfer gate is used to drive the slave. The power numbers are given at the clock frequency both when the output is stable and when it changes. The setup and hold times are the maximum for pin d transition times up to 1500ps and for clock pin cp up to 670ps. The fanout 4 effort value is when the z output drives the cp input, as in a ripple counter.
z:ff(cp,d) cell width power Generic 0.13um typical timing (ps & ps/fF), pin cp-z.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap   Prop Ramp Setup Hold
dfnt1v0x2 6.0 144 7.92 2.12 clock only  13.4 cp  2.3f Rise 184  2.13 199  191
state change  39.1 d  2.4f Fall 205  1.67 307 147
dfnt1v0x2
 
FO4 Effort
cp 2.92
dfnt1v0x2 schematic dfnt1v0x2 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  23 DEC 2008