mxn2 standard cell family

 2-way multiplexers
mxn2 symbol
Two types of non-inverting 2-way muxes. The v0 muxes are minimum width but slow on pin s as the inverting path to pin z has three stage delays. The v2 mux uses transfer gates for the best speed but is bigger.
z:((a0*s')+(a1*s)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin s.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
mxn2v0x05 2.7  64 3.52  0.76  17.0  3.6f 124  5.01 124  4.01
mxn2v0x1 2.7  64 3.52 1.03  21.8  4.3f 119  3.33 126  2.65
mxn2v2x1 4.0  96 5.28 1.49  19.3  5.3f  55  3.41  59  2.58
mxn2v0x05
 
Effort
FO4 Log.
a0 /\
¯_ 2.37
a1 /\
¯_ 2.27
s /\ 2.98 1.64
¯_ 2.45
mxn2v0x05 schematic mxn2v0x05 standard cell layout
mxn2v0x1
 
Effort
FO4 Log.
a0 /\
¯_ 2.21
a1 /\
¯_ 2.15
s /\ 2.77 1.27
¯_ 2.23
mxn2v0x1 schematic mxn2v0x1 standard cell layout
mxn2v2x1
 
Effort
FO4 Log.
a0 /\
¯_ 1.86
a1 /\
¯_ 1.84
s /\ 1.74 2.21
¯_ 1.73
mxn2v2x1 schematic mxn2v2x1 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008