nd3 standard cell family

 3-I/P NAND gate
nd3 symbol
5 cells with their P/N ratio set to 2.33. The fastest speed occurs when the shape factor r=√(KP÷KN×µ). For a 3-NAND gate, we use KP=1; KN=7/3, and µ=9/4, giving r=√(27/28). We chooose to set r=1 instead, so the P/N ratio is close to the maximum speed, as well as giving balanced rise and fall drive strengths, with the convenience of the P and N transistors having the same size.
z:(a*b*c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd3v0x05 1.7  40 2.20  0.46   5.8  2.4f  52  5.94  41  5.09
nd3v0x1 1.7  40 2.20  0.92  10.2  4.3f  50  2.97  38  2.54
nd3v0x2 2.7  64 3.52 1.29  13.2  6.0f  48  2.12  37  1.83
nd3v5x2 2.7  64 3.52 1.29  12.9  6.2f  48  2.12  36  1.83
nd3v0x3 3.0  72 3.96 1.85  18.1  8.6f  47  1.48  36  1.28
nd3v5x3 3.0  72 3.96 1.85  17.8  8.5f  47  1.48  36  1.28
nd3v0x4 3.7  88 4.84 2.31  24.2 11.1f  49  1.19  38  1.02
nd3v5x4 4.7 112 6.16 2.77  27.1 12.4f  47  0.99  36  0.85
nd3v0x6 5.7 136 7.48 3.70  37.0 17.6f  48  0.74  36  0.64
nd3v5x6 6.0 144 7.92 3.73  35.1 16.6f  46  0.73  35  0.64
nd3v6x6 5.3 128 7.04 3.73  36.7 16.6f  47  0.73  36  0.64
nd3v0x05
 
Effort
FO4 Log.
a /\ 1.55 1.54
¯_
b /\ 1.54 1.62
¯_
c /\ 1.42 1.53
¯_
nd3v0x05 schematic nd3v0x05 standard cell layout
nd3v0x1
 
Effort
FO4 Log.
a /\ 1.47 1.45
¯_
b /\ 1.43 1.47
¯_
c /\ 1.32 1.39
¯_
nd3v0x1 schematic nd3v0x1 standard cell layout
nd3v0x2
 
Effort
FO4 Log.
a /\ 1.48 1.50
¯_
b /\ 1.40 1.45
¯_
c /\ 1.29 1.39
¯_
nd3v0x2 schematic nd3v0x2 standard cell layout
nd3v5x2
 
Effort
FO4 Log.
a /\ 1.49 1.53
¯_
b /\ 1.40 1.47
¯_
c /\ 1.30 1.42
¯_
nd3v5x2 schematic nd3v5x2 standard cell layout
nd3v0x3
 
Effort
FO4 Log.
a /\ 1.47 1.51
¯_
b /\ 1.40 1.48
¯_
c /\ 1.28 1.38
¯_
nd3v0x3 schematic nd3v0x3 standard cell layout
nd3v5x3
 
Effort
FO4 Log.
a /\ 1.44 1.44
¯_
b /\ 1.40 1.47
¯_
c /\ 1.26 1.36
¯_
nd3v5x3 schematic nd3v5x3 standard cell layout
nd3v0x4
 
Effort
FO4 Log.
a /\ 1.47 1.47
¯_
b /\ 1.44 1.52
¯_
c /\ 1.32 1.43
¯_
nd3v0x4 schematic nd3v0x4 standard cell layout
nd3v5x4
 
Effort
FO4 Log.
a /\ 1.44 1.39
¯_
b /\ 1.37 1.37
¯_
c /\ 1.25 1.33
¯_
nd3v5x4 schematic nd3v5x4 standard cell layout
nd3v0x6
 
Effort
FO4 Log.
a /\ 1.48 1.51
¯_
b /\ 1.42 1.49
¯_
c /\ 1.30 1.41
¯_
nd3v0x6 schematic nd3v0x6 standard cell layout
nd3v5x6
 
Effort
FO4 Log.
a /\ 1.44 1.39
¯_
b /\ 1.36 1.37
¯_
c /\ 1.23 1.32
¯_
nd3v5x6 schematic nd3v5x6 standard cell layout
nd3v6x6
 
Effort
FO4 Log.
a /\ 1.45 1.42
¯_
b /\ 1.40 1.43
¯_
c /\ 1.25 1.32
¯_
nd3v6x6 schematic nd3v6x6 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008