aoi211 standard cell family

 2-AND into 3-NOR gate
aoi211 symbol
4 cells with a P/N ratio of about 2. The width of the N-transistors connected to pins b and c are designed to have a similar conductivity to the two series N-transistors connected to pins a1 and a2, so that there is a consistent output drive capability. Cell aoi211v5x05 is a layout variant of aoi211v0x05.
z:((a1*a2)+b+c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aoi211v0x05 2.0  48 2.64  0.57  18.3  4.1f  92  6.31  73  4.42
aoi211v5x05 2.3  56 3.08  0.55  17.9  4.0f  93  6.52  72  4.34
aoi211v0x1 3.7  88 4.84 1.07  33.7  8.1f  86  3.15  72  2.31
aoi211v0x2 7.0 168 9.24 2.15  64.4 15.5f  83  1.57  70  1.14
aoi211v0x05
 
Effort
FO4 Log.
a1 /\ 2.52 2.62
¯_
a2 /\ 2.44 2.57
¯_
b /\ 2.07 2.23
¯_
c /\ 1.82 2.19
¯_
aoi211v0x05 schematic aoi211v0x05 standard cell layout
aoi211v5x05
 
Effort
FO4 Log.
a1 /\ 2.52 2.61
¯_
a2 /\ 2.44 2.54
¯_
b /\ 2.04 2.18
¯_
c /\ 1.80 2.12
¯_
aoi211v5x05 schematic aoi211v5x05 standard cell layout
aoi211v0x1
 
Effort
FO4 Log.
a1 /\ 2.41 2.53
¯_
a2 /\ 2.39 2.56
¯_
b /\ 2.06 2.26
¯_
c /\ 1.73 2.11
¯_
aoi211v0x1 schematic aoi211v0x1 standard cell layout
aoi211v0x2
 
Effort
FO4 Log.
a1 /\ 2.38 2.52
¯_
a2 /\ 2.31 2.46
¯_
b /\ 2.00 2.18
¯_
c /\ 1.71 2.10
¯_
aoi211v0x2 schematic aoi211v0x2 standard cell layout
Web data book for the wsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008