nr4 standard cell family

 4-I/P NOR gate
nr4 symbol
The P/N ratio has been kept as close to 2 as possible for balanced output skew, even if this is not the fastest configuration, except for the nr4v1x05 which is fast but with unbalanced output skews.
z:(a+b+c+d)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr4v1x05 2.3  56 3.08  0.53   6.8  3.1f  61 10.62  46  3.93
nr4v0x1 3.3  80 4.40  0.77   9.3  5.2f  46  5.40  55  3.89
nr4v0x2 4.7 112 6.16 1.42  17.0 10.1f  47  2.95  56  2.12
nr4v1x05
 
Effort
FO4 Log.
a /\ 2.69 2.79
¯_
b /\ 2.66 2.87
¯_
c /\ 2.41 2.73
¯_
d /\ 2.06 2.64
¯_
nr4v1x05 schematic nr4v1x05 standard cell layout
nr4v0x1
 
Effort
FO4 Log.
a /\ 3.21 3.47
¯_
b /\ 2.96 3.20
¯_
c /\ 2.56 2.93
¯_
d /\ 2.10 2.79
¯_
nr4v0x1 schematic nr4v0x1 standard cell layout
nr4v0x2
 
Effort
FO4 Log.
a /\ 2.99 3.11
¯_
b /\ 2.83 3.01
¯_
c /\ 2.57 2.98
¯_
d /\ 2.20 2.97
¯_
nr4v0x2 schematic nr4v0x2 standard cell layout
Web data book for the wsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008