2-NAND and 2-NOR Gates with Inverting Input - nd2a, nr2a

	gate count 1480 number of cells 666 number of library cells 76 number of used cells 34 max fanin 17 max input capacitance 187 max internal fanout 34 critical path 0fF 2300 critical path 6fF 2963
	nd2a
	nr2a

These two cells are included in the CyHP (Compact yet High Performance) library of 20 cells. This paper is one of only three known to discuss the issue of which cells to include in a standard cell library.

The merits of the nr2a for speed are dubious. Either the critical path passes thru the non-inverting path, in which case a 2-AND is faster. Or it passes thru the inverting path, in which case a regular 2-NOR is just as good.

The nd2a can be useful for speed since if the critical path passes thru the non-inverting path, it will be faster than a conventional 2-OR gate.

Both gates are useful in saving area.

For the BOOG synthesis, the nd2a delay is set equal to the AND gates, at 400ps. The nr2a delay is set larger than the other non-inverting gates at 600ps. Since the nr2a is slower than a 2-AND gate, it is important for BOOG to see a timing difference. Otherwise the nr2a will be used where a 2-AND is faster, with a reduction in multiplier performance.

In this synthesis, only the nr2a is chosen by BOOG, and then just one occurence. It can appear on the critical path, since in the final netlist is has been buffered up to an nr2av0x2.

A netlist version of the or3 and or4 gates has been made, to be used by LOON if its timing is better than the or3v0x2 or or4v0x2. The nd2a allows an optimised path from one favoured input to the output.

	or3 netlist using nd2a
	or4 netlist using nd2a

The LOON optimisation chooses one or4 and one or3 netlist, which means that the final circuit contains two nd2av0x2 cells.
Note that this kind of Boolean optimisation, swapping an or4 with a nr3 and nda2 netlist won't be done unaided by LOON. You have to make your own netlists, calculate their timing and put it into a VBE file so that LOON will see them as library primitives and use them for circuit optimisation like any othe library cell.

Afterwards the VBE is substituted with the netlist to give a final circuit which uses only real library cells.