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gate count 1362 number of cells 553 number of library cells 91 number of used cells 38 max fanin 17 max input capacitance 187 max internal fanout 34 critical path 0fF 2280 critical path 6fF 2908 |
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xaoi21
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xaon21
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xooi21
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xoon21
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Now we examine the multiplier netlist to see whether possible new logic gates will be selected by BOOG.
Looking at the netlist with XSCH shows gate combinations like the one below:
The combinations of 2-NOR+2-XOR and 2-AND+2-XOR
could be combined into a single gate with 3 inputs.
Four gate types like this can be tried out, shown
by the symbols above right. In fact,
these netlists have already been used as macros in
the previous experiments.
Extending an XOR or XNOR gate by turning one of its inputs into a 2-AND or a 2-OR is relatively straight forward. An inverter connected to one of the inputs is changed to a 2-NAND or a 2-NOR gate. Implementing it as a gate netlist is also efficient, since inverting 2-NAND and 2-NOR gates can be used.
The four new cells are added to the list for BOOG. The timing of the xaoi21 and xaon21 gates is made the same as the regular XOR and XNOR gates at 75ps. The timing of the xooi21 and xoon21 gates is set to 100ps, since the input gate structure is slower.
These cells give general benefits in terms of speed, area and connectivity through a reduced number of cells and pin connections. The critical path shows an improvement from 2960 to 2908, or 1.8%; the area improves by 8.0% and the porosity increases by one percentage point from 53% to 54%.
BOOG chooses two of the xaon21, eight of the xoon21 and 102 of the xooi21 cells, which reduces the total number of cells from 666 down to 553.
The conclusion is that these AND/OR into XOR/XNOR gates are useful additions to the library. The critical path is shown below.
fanout -- delay--
x 1 17 187
1 nd4v0x1 1 d->z 288 101
2 oai21v0x2 4 b->z 424 136
3 iv1v0x4 1 a->z 473 49
4 oai21v0x2 4 a2->z 612 139
5 iv1v0x4 1 a->z 661 49
6 oai21v0x2 4 a2->z 800 139
7 iv1v0x4 1 a->z 849 49
8 oai21v0x2 4 a2->z 987 138
9 iv1v0x4 1 a->z 1036 49
10 oai21v0x2 4 a2->z 1172 136
11 iv1v0x4 1 a->z 1221 49
12 oai21v0x2 4 a2->z 1356 135
13 iv1v0x4 1 a->z 1406 50
14 oai21v0x2 5 a2->z 1572 166
15 xor2v0x1 1 b->z 1685 113
16 xor2v0x2 1 a->z 1796 111
17 xnr2v0x2 1 b->z 1901 105
18 cgi2v0x2 2 b->z 2011 110
19 iv1v0x4 1 a->z 2070 59
20 cgi2v0x2 2 a->z 2182 112
21 iv1v0x4 1 a->z 2232 50
22 cgi2v0x2 2 c->z 2337 105
23 iv1v0x4 1 a->z 2387 50
24 cgi2v0x2 2 c->z 2471 84
25 an2v0x2 2 b->z 2591 120
26 an2v0x2 2 b->z 2737 146
27 xaon21v0x2 0 a1->z 2908 171
r 15 |
| Table of synthesis results | |||||||
| critical path (ps) | gate count | cell count | porosity | library cells | used cells | ||
| synthesis 1 | 4279 | 1561 | 923 | 43% | 9 | 8 | basic inverters, NAND & NOR gates |
| synthesis 2 | 4236 | 1472 | 792 | 45% | 15 | 12 | AND & OR gates |
| synthesis 3 | 4157 | 1357 | 696 | 46% | 19 | 16 | AOI & OAI gates, 2/1 and 2/2 |
| synthesis 4 | 4157 | 1357 | 696 | 46% | 20 | 16 | mxi2 2-way inverting mux |
| synthesis 5 | 3983 | 1343 | 668 | 48% | 21 | 16 | cgi2 carry generator inverting |
| synthesis 6 | 3948 | 1352 | 668 | 48% | 28 | 18 | inverters with multiple drive strengths |
| synthesis 7 | 3061 | 1433 | 666 | 51% | 70 | 27 | x2 drive strengths for all functions |
| synthesis 8 | 3056 | 1456 | 666 | 52% | 70 | 30 | BOOG with x1 drive strengths |
| synthesis 9 | 2960 | 1476 | 666 | 53% | 70 | 32 | BOOG with x05 drive strengths |
| synthesis 10 | 2963 | 1480 | 666 | 53% | 76 | 34 | nd2a and nr2a cells |
| synthesis 11 | 2963 | 1480 | 666 | 53% | 79 | 34 | nd2ab type of 2-OR |
| CyHP library | 3778 | 1539 | 832 | 46% | 18 | 17 | Minimum size library |
| synthesis 12 | 2908 | 1362 | 553 | 54% | 91 | 38 | AND/OR into XOR/XNOR |
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