gate count 1343 number of cells 668 number of library cells 21 number of used cells 16 max fanin 17 max input capacitance 187 max internal fanout 34 critical path 0fF 2766 critical path 6fF 3983
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gate count 1343 number of cells 668 number of library cells 21 number of used cells 16 max fanin 17 max input capacitance 187 max internal fanout 34 critical path 0fF 2766 critical path 6fF 3983 |
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The inclusion of this cell in a library is essential to provide high performance for arithmetic functions. One pin, pin c in the vsclib, is connected to only two transistors and provides the fastest path through the gate. The cells used are shown below. There are only 21 cgi2 cells, but they appear all along the critical path.
an2v0x2 5 aoi21v0x1 1 aoi22v0x1 28 cgi2v0x1 21 iv1v0x2 83 nd2v0x2 3 nd3v0x1 2 nd4v0x1 28 nr2v0x1 183 nr3v0x05 8 oai21v0x1 31 or2v0x2 3 or3v3x2 1 or4v3x2 1 xnr2v0x1 62 xor2v0x1 206 |
The critical path is now at 29 cells, down from 31 previously and 33 with the initial library of basic inverting gates. The circuit is 4.2% faster and 1.0% smaller than one without cgi2 gates.
fanout -- delay--
y 1 16 176
1 iv1v0x2 25 a->z 685 509
2 nr2v0x1 1 b->z 774 89
3 xor2v0x1 1 b->z 881 107
4 xnr2v0x1 1 b->z 983 102
5 cgi2v0x1 3 c->z 1160 177
6 iv1v0x2 1 a->z 1216 56
7 cgi2v0x1 3 c->z 1400 184
8 iv1v0x2 1 a->z 1456 56
9 cgi2v0x1 3 c->z 1640 184
10 iv1v0x2 1 a->z 1704 64
11 cgi2v0x1 3 b->z 1899 195
12 iv1v0x2 1 a->z 1963 64
13 cgi2v0x1 3 b->z 2158 195
14 iv1v0x2 1 a->z 2222 64
15 cgi2v0x1 3 b->z 2409 187
16 iv1v0x2 1 a->z 2465 56
17 cgi2v0x1 3 c->z 2642 177
18 iv1v0x2 2 a->z 2717 75
19 iv1v0x2 1 a->z 2775 58
20 nd2v0x2 1 b->z 2836 61
21 oai21v0x1 3 b->z 3009 173
22 xnr2v0x1 1 b->z 3112 103
23 cgi2v0x1 2 c->z 3255 143
24 iv1v0x2 1 a->z 3311 56
25 cgi2v0x1 2 c->z 3443 132
26 an2v0x2 2 b->z 3567 124
27 an2v0x2 2 b->z 3694 127
28 nd2v0x2 1 b->z 3763 69
29 xnr2v0x1 0 b->z 3983 220
r 15 |
| Table of synthesis results | |||||||
| critical path (ps) | gate count | cell count | porosity | library cells | used cells | ||
| synthesis 1 | 4279 | 1561 | 923 | 43% | 9 | 8 | basic inverters, NAND & NOR gates |
| synthesis 2 | 4236 | 1472 | 792 | 45% | 15 | 12 | AND & OR gates |
| synthesis 3 | 4157 | 1357 | 696 | 46% | 19 | 16 | AOI & OAI gates, 2/1 and 2/2 |
| synthesis 4 | 4157 | 1357 | 696 | 46% | 20 | 16 | mxi2 2-way inverting mux |
| synthesis 5 | 3983 | 1343 | 668 | 48% | 21 | 16 | cgi2 carry generator inverting |
A trick has to be used with the Alliance synthesis software in order for the cgi2 function to be used properly.
For BOOG sixteen different cells are included in the library, each of which has the logical function expressed slightly differently. Two versions are shown below as an example:
z <= not ((a or (c and b)) and (c or b)) after 1100 ps; z <= (not b and (not a or not c)) or (not a and not c) after 1100 ps;
When LOON is first used, the different cgi2 cells are all mapped to a cgi2v0x1 by a netlist like the one below:
entity cgi2v6x1 is
port (
a : in bit;
b : in bit;
c : in bit;
z : out bit;
vdd : in bit;
vss : in bit
);
end cgi2v6x1;
architecture structural of cgi2v6x1 is
Component cgi2v0x1
port (
a : in bit;
b : in bit;
c : in bit;
z : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
z : cgi2v0x1
port map (
a => a,
b => b,
c => c,
z => z,
vdd => vdd,
vss => vss
);
end structural;
Then the logical function used by the two LOON libraries is slightly different. The 0fF wireload library uses
z <= not ((c or (b and a)) and (b or a)) after 1100 ps;
and the 6fF library uses
z <= not ((c or (a and b)) and (a or b)) after 1100 ps;
When the target library is switched between the 0fF and 6fF timing, this function switch allows LOON to connect the critical path to the c input of the cgi2, which is the quickest one. Otherwise one can find that the critical path is routed through one of the slower pins.
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