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gate count 1433 number of cells 666 number of library cells 70 number of used cells 27 max fanin 17 max input capacitance 211 max internal fanout 34 critical path 0fF 2434 critical path 6fF 3061 |
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All of the 21 functions are provided in 3 drive strengths: x05, x1 and x2. The inverters have more drive strengths, 8 in all, giving 20×3+8=68 cells. Then the or3 and or4 gates have a second x2 drive strength which is slower but smaller, giving a total of 70 cells. The table below lists each function with the drive strength initially used by BOOG in the first column, followed by the other drive strengths and their usage after optimisation by LOON.
an2v0x2 5 an2v0x05 0 an2v0x1 0 aoi21v0x1 1 aoi21v0x05 0 aoi21v0x2 0 aoi22v0x1 27 aoi22v0x05 0 aoi22v0x2 1 cgi2v0x1 7 cgi2v0x05 0 cgi2v0x2 14 iv1v0x2 47 iv1v0x05 0 iv1v0x1 0 iv1v0x3 7 iv1v0x4 14 iv1v0x6 0 iv1v0x8 1 iv1v0x12 12 nd2v0x2 3 nd2v0x05 0 nd2v0x1 0 nd3v0x1 2 nd3v0x05 0 nd3v0x2 0 nd4v0x1 28 nd4v0x05 0 nd4v0x2 0 nr2v0x1 183 nr2v1x05 0 nr2v0x2 1 nr3v0x05 8 nr3v0x1 0 nr3v0x2 0 oai21v0x1 14 oai21v0x05 0 oai21v0x2 17 or2v0x2 2 or2v0x05 0 or2v0x1 0 or3v3x2 1 or3v0x05 0 or3v0x1 0 or3v0x2 0 or4v3x2 1 or4v0x05 0 or4v0x1 0 or4v0x2 0 xnr2v0x1 45 xnr2v0x05 12 xnr2v0x2 4 xor2v0x1 206 xor2v0x05 0 xor2v0x2 1 |
Not one weaker drive strength from any gate has been selected by LOON. The xnr2v0x05 cells come from a built-up gate used to buffer the lower order outputs. These outputs start off after BOOG as an xor2v0x1, which are then switched to a minimum size xnr2 gate and inverter by a script. This minimises the input pin capacitance while providing an x2 drive strength on outputs off of the critical path, an optimisation which LOON is unable to do.
The critical path with three available drive strengths is 22% faster than before at the cost of a 6% area increase and shows a more even distribution of delays between the gates.
fanout -- delay--
y 1 16 206
1 nd4v0x1 1 b->z 314 108
2 oai21v0x2 4 b->z 449 135
3 iv1v0x4 1 a->z 498 49
4 oai21v0x2 4 a2->z 653 155
5 iv1v0x4 1 a->z 702 49
6 oai21v0x2 4 a2->z 853 151
7 iv1v0x4 1 a->z 902 49
8 oai21v0x2 4 a2->z 1054 152
9 iv1v0x4 1 a->z 1103 49
10 oai21v0x2 4 a2->z 1246 143
11 iv1v0x3 1 a->z 1301 55
12 oai21v0x2 4 a2->z 1440 139
13 iv1v0x2 1 a->z 1506 66
14 oai21v0x2 5 a2->z 1687 181
15 xnr2v0x2 1 a->z 1789 102
16 cgi2v0x2 3 c->z 1911 122
17 iv1v0x4 2 a->z 1965 54
18 iv1v0x2 1 a->z 2024 59
19 nd2v0x2 1 b->z 2091 67
20 oai21v0x2 3 b->z 2202 111
21 xnr2v0x1 1 a->z 2337 135
22 cgi2v0x2 2 c->z 2439 102
23 iv1v0x4 1 a->z 2489 50
24 cgi2v0x2 2 c->z 2577 88
25 an2v0x2 2 b->z 2700 123
26 an2v0x2 2 b->z 2833 133
27 nd2v0x2 1 b->z 2909 76
28 xnr2v0x2 0 a->z 3061 152
r 15 |
The next experiment will be to synthesise with BOOG, changing the initial x2 drive strengths to x1, and then use LOON to buffer up where needed. Since the gates off the critical path are smaller, the critical path itself should be faster, even if the gates on the critical path use only the stronger drive strengths.
| Table of synthesis results | |||||||
| critical path (ps) | gate count | cell count | porosity | library cells | used cells | ||
| synthesis 1 | 4279 | 1561 | 923 | 43% | 9 | 8 | basic inverters, NAND & NOR gates |
| synthesis 2 | 4236 | 1472 | 792 | 45% | 15 | 12 | AND & OR gates |
| synthesis 3 | 4157 | 1357 | 696 | 46% | 19 | 16 | AOI & OAI gates, 2/1 and 2/2 |
| synthesis 4 | 4157 | 1357 | 696 | 46% | 20 | 16 | mxi2 2-way inverting mux |
| synthesis 5 | 3983 | 1343 | 668 | 48% | 21 | 16 | cgi2 carry generator inverting |
| synthesis 6 | 3948 | 1352 | 668 | 48% | 28 | 18 | inverters with multiple drive strengths |
| synthesis 7 | 3061 | 1433 | 666 | 51% | 70 | 27 | x2 drive strengths for all functions |
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