## Logical Effort of NAND Gates

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In order to calculate the logical effort of a NAND gate, we size the transistors so that their conductance is the same as the single transistors in a reference inverter. There is a single P transistor between the output and Vdd, so this remains unchanged. But the N transistors are in series, and must be increased in size so that they have the same conductance as a single N transistor. We define the amount by which the transistor must be increased as KN, the N transistor conductivity coefficient.

In the book Logical Effort, Ohm's law is used so that KN is 2 for a 2-NAND gate, 3 for a 3-NAND gate and 4 for a 4-NAND gate. The book recognises that this is a simplification, because velocity saturation of the carriers means that series combinations of N transistors are more conductive than a single one.

Following the Logical Effort book example, we apply Ohm's law and set µ=2. We can see that the ratio of the input capacitance of 2-, 3- and 4-input NAND gates compared to a reference inverter is (2+2)/(2+1), (2+3)/(2+1) and (2+4)/(2+1).

 gate INV 2-NAND 3-NAND 4-NAND input cap 3 4 5 6 logical effort g 1 4/3 5/3 6/3 1.00 1.33 1.67 2.00

### Selecting the P:N Transistor Ratio for 2/3/4 Input NAND Gates

Here we consider a more general case where the NAND gate can have a P:N transistor ratio of γ; the N:P conductivity = µ; and the value for KN of the NAND gates need not be equal to the number of series N transistors. A 2-input NAND gate with the equivalent drive of an inverter with (P=γ,N=1) has (P=γ, N=KN). This matches the conductivity of the N transistor of the reference inverter, so that the falling logical effort
gd = (KN+γ)/(1+ µ)
For the rising logical effort, we scale the P transistor to P=µ, giving N=KN·µ/γ, so that
gu = ( µ+KN· µ/γ)/(1+µ)
The logical effort g is then:
g = ½×(γ+KN+ µ+ KN· µ/γ)/(1+µ)

For the vsclib, the values used are µ=2.25 and KN=(5/3, 7/3, 9/3) for 2-,3-,4-input NAND gates.

The fastest NAND gate is when
dg/dγ = 0 = 1-KN· µ2
from which γ = √(KN·µ) for the fastest NAND gates.

Some values of logical effort for 2-NAND gates with different values of γ, assuming that µ=2.25, and KN=5/3 are:

 P:N ratio γ 1 1.5 1.94 2 2.25 2.5 3 4 logical effort g 1.33 1.22 1.2 1.2 1.21 1.22 1.26 1.36

The minimum logical effort occurs when γ=√(5/3×2.25)=1.94. Since the logical effort when γ=2 is practically the same, we choose γ=2 for 2-NAND gates in the vsclib.

The table below shows some values of logical effort for 3-NAND gates with different values of γ, assuming that µ=2.25, and KN=7/3.

 P:N ratio γ 1 1.5 2 2.29 2.33 2.5 3 4 logical effort g 1.67 1.47 1.42 1.41 1.41 1.41 1.44 1.52

The minimum logical effort occurs when γ=√(7/3×2.25)=2.29. Since the logical effort when γ=2.33 is practically the same, and γ=2.33 corresponds to setting the P and N transistors equal in size, we choose γ=2.33 for 3-NAND gates in the vsclib.

The table below shows some values of logical effort for 4-NAND gates with different values of γ, assuming that µ=2.25, and KN=3.

 P:N ratio γ 1 1.5 2 2.25 2.5 2.6 3 4 logical effort g 2 1.73 1.63 1.62 1.61 1.61 1.62 1.68

The minimum logical effort occurs when γ=√(3×2.25)=2.60. Since the logical effort when γ=2.5 is practically the same, and γ=2.5 has the same discrepancy in output drive strengths as γ=2 (but the other way round), and &gamma=2 has been chosen as the normal P:N transistor ratio for the vsclib, we choose γ=2.5 for 4-NAND gates.

The vsclib then is using values of γ and logical effort g that are significantly different to the ones used in the book Logical Effort. We can check them using the example in Table 5.4 from the book, which takes an average logical effort from a range of 9 processes and voltages.

 Gate 2-NAND 3-NAND 4-NAND Logical Effort theoretical g 1.33 1.67 2.00 Theoretical g for vsclib 1.20 1.41 1.61 Average g of 9 processes 1.18 1.39 1.62

From this we can conclude that the choices made for the N transistor conductivity coefficients, KN for the vsclib NAND gates are OK.