There are 5 families of pharosc standard cell libraries. Their cell heights and space for P and N transistors are shown below.

vsclib 72λ tall standard cell, P=28λ, N=20λ
wsclib 80λ tall standard cell, P=28λ, N=20λ
vxlib 100λ tall standard cell, P=39λ, N=32λ
rgalib 88λ tall gate array, P=28λ, N=20λ
vgalib 88λ tall gate array, P=26λ, N=18λ

All the libraries have been drawn with Alliance software Graal, converted to 0.13µm CIF and GDS, extracted to Spice and characterised with Winspice using publicly available 0.13µm Spice models. The layout uses the pharosc rule set, similar to the MOSIS rules but a better fit to DSM technologies.

The vxlib actually uses slightly larger pharosc rules because it has been designed for compatibility with the Alliance sxlib.

Each library has a Synopsys Liberty format timing file for synthesis which uses table lookup models.

There are 322 cells in the vsclib and wsclib including a D flip‑flop and latch, and multiple drive strength cells, so these libraries can be used for quite sophisticated work. The wsclib is the same as the vsclib but with continuous substrate and ground ties at the top and bottom of each cell.

The vxlib contains 96 combinatorial cells which are compatible with the Alliance sxlib. The routing pitch is 10λ instead of the 8λ used for the vsclib and wsclib.

The rgalib and vgalib are small 20 cell gate array libraries containing a minimum number of combinatorial cells. They use a routing pitch of 8λ

All the libraries have a nice on-line web data book (top right).

The cells make full use of the available transistor space and have been designed for speed and density comparable to commercial standard cell libraries. None of the cells use internal metal-2 crossovers. The basic 2-XOR cell widths in lambda are

vsclib wsclib vxlib rgalib vgalib
64 64 70 96 96

0.13um vgalib data sheet example
Example 0.13µm vgalib data sheet

vsclib 0.13um 2-XOR gate
vsclib 0.13µm technology 2-XOR gate GDS file visualised in klayout