We develop a flow for synthesis with the sclib which can give faster netlists than the conventional Alliance synthesis flow, and test it on an 8×8 multiplier.

Although tested here with the sclib, the flow works with the other Alliance libraries. This will be documented soon on this web site.

The flow consists of

  • Correcting the area values in the library files
  • Correcting some small mistakes in the library files
  • Setting appropriate values for input impedance and output load
  • Using the best optimisation levels for the synthesis programs BOOG and LOON
  • BOOG synthesis with a minimum drive strength library
  • Support for estimated wireload capacitance
  • Fanin reduction
  • Adding logic macros
  • Adding some analysis scripts

The result is to replace the standard Alliance synthesis flow of

1 $ boog -l lax in_file boog_file
2 $ loon -l lax boog_file out_file           

with a similar one

1 $ boog -l lax in_file boog_file
2 $ ./loop_buf_loon -l lax boog_file out_file

The script loop_buf_loon uses successive iterations of loon to find the fastest possible netlist and writes it to out_file.vst.

The timing is used as provided. There has been no characterisation with the generic 0.13µm technology that has been used for the other standard cell libraries on this site.

According to the documentation, the sclib timing comes from a 0.5µm technology. The spice models are not provided, so no changes or checks can be made. We have to live with the timing as-is.

The logic description for each cell is in a VBE file, shown in the example on the right. The synthesis software uses the parameters:
pin capacitance,
rising and falling Prop delays,
output rising and falling resistances
and logic function
to synthesise the logic description. Timing is calculated using the classic CMOS equation


A single delay is used for each cell, which is the average of the rise and fall delays. An option to the synthesis programs BOOG and LOON allows the user to make a trade off between area and speed.

Setting a simulator delay

These cell parameters are only used for the synthesis. The Alliance simulator ASIMUT uses the timing in the after clause of the logic function. The sclib files don't have an after clause which means a zero delay is used. To give a more realistic simulation, a delay of 1000ps has been added to all the files. This is done with a script.

$ sed -i 's/^ *\([^ ][^ ]*\)  *<= *\([^;][^;]*\); *$/  \1 <= \2 after 1000ps;/' ${cell}.vbe

The sxlib logic description files all have a delay set with the after clause. The pharosc libraries have it set to the delay of each gate driving a 4X load. It is quite complicated to calculate this value, so that is why a simple number of 1000ps has been used instead for the sclib.

Example of an sclib logic file description, na2_y.vbe
-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `na2_y`
--		date : Wed Oct  7 12:13:01 1998

    CONSTANT area : NATURAL := 756;
    CONSTANT transistors : NATURAL := 4;
    CONSTANT cin_i1 : NATURAL := 35;
    CONSTANT cin_i0 : NATURAL := 35;
    CONSTANT tplh_i0_f : NATURAL := 400;
    CONSTANT rup_i0_f : NATURAL := 2450;
    CONSTANT tphl_i0_f : NATURAL := 269;
    CONSTANT rdown_i0_f : NATURAL := 2340;
    CONSTANT tplh_i1_f : NATURAL := 504;
    CONSTANT rup_i1_f : NATURAL := 2450;
    CONSTANT tphl_i1_f : NATURAL := 196;
    CONSTANT rdown_i1_f : NATURAL := 2340
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
END na2_y;


  ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on na2_y"
  f <= (i1 nand i0) after 1000ps;