Chapter

Section

LOON synthesis optimises a netlist for speed and area, but it doesn't change its structure. It will never for example change a weak 2-AND gate to a 2-NAND followed by a large drive strength inverter. This means that if

  1. the library has few functions with high drive strengths and
  2. the netlist has high fanout nodes driven by one of these weak cells

then it will be slow because the synthesis tools cannot replace the cell with something beefier.

sclib oai21 cell In the critical path on the right, the 7 nodes with the biggest delay are all high fanout nets driven by an noa3_y (which is an oai21), sclib oai31 cell or an noa4_y (which is an oai31). The 5 noa4_y paths are from pin i3 to pin f, so it is possible that a separate 3-OR and high drive 2-NAND macro would be quicker.

sclib high drive oai31 macro

Creating the macro

To create a macro, we need to:

  1. calculate the timing of the composite function
  2. write a VBE file with this timing
  3. write a VST file with the netlist

I calculate the timing with a spreadsheet. It is slow to set up, but writing a script or program to do the calculation is not simple. The spreadsheet for the timing of an noa4p_y made with a 3-OR gate o3_y and a high drive 2-NAND na2p_y is shown on the right for both 0fF and 45fF wireloads.

The file noa4_y.vbe is copied to noa4p_y.vbe and manually edited with the new timing numbers. This file is added to the directory pointed to by MBK_TARGET_LIB used by LOON (below right).

A netlist of the function (below) is created and put into a directory on the MBK_CATA_LIB search path. After LOON has selected the cell, the netlist is flattened to the catalog and the cell noa4p_y.vbe replaced by its netlist found in the catalog search path.

It's easy to make a mistake when writing the VST netlist, but it can be checked with XSCH.

$ xsch -l noa4p_y

This is the schematic shown above.

 
noa4p_y.vst netlist written by hand.

entity noa4p_y is
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      f   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end noa4p_y;
architecture structural of noa4p_y is
Component na2p_y
   port (
      i0  : in      bit;
      i1  : in      bit;
      f   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;
Component o3_y
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      t   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;
signal t : bit;
begin
t : o3_y
   port map (
      i0  => i0,
      i1  => i1,
      i2  => i2,
      t   => t,
      vdd => vdd,
      vss => vss
   );
f : na2p_y
   port map (
      i0  => i3,
      i1  => t,
      f   => f,
      vdd => vdd,
      vss => vss
   );
end structural;

#     y 1      41                 4242
#  1  nao3_y    1  i1->f    5071   829   nao3_y_6_ins            nao3_y_6_sig
#  2  noa3_y    6  i0->f    7262  2191   rtlcarry_12_2_ins       rtlcarry_12_2
#  3  noa3_y    1  i0->f    7937   675   noa3_y_17_ins           noa3_y_17_sig
#  4  noa4_y    6  i3->f   10511  2574   rtlcarry_12_3_ins       rtlcarry_12_3
#  5  noa3_y    1  i0->f   11185   674   noa3_y_18_ins           noa3_y_18_sig
#  6  noa4_y    7  i3->f   14175  2990   rtlcarry_12_4_ins       rtlcarry_12_4
#  7  noa3_y    1  i0->f   14849   674   noa3_y_19_ins           noa3_y_19_sig
#  8  noa4_y    6  i3->f   17404  2555   rtlcarry_12_5_ins       rtlcarry_12_5
#  9  nao3_y    1  i2->f   18185   781   nao3_y_7_ins            nao3_y_7_sig
# 10  noa3_y    6  i0->f   20391  2206   rtlcarry_12_6_ins       rtlcarry_12_6
# 11  noa3_y    1  i0->f   21066   675   noa3_y_20_ins           noa3_y_20_sig
# 12  noa4_y    7  i3->f   24062  2996   rtlcarry_12_7_ins       rtlcarry_12_7
# 13  noa3_y    1  i0->f   24736   674   noa3_y_21_ins           noa3_y_21_sig
# 14  noa4_y    6  i3->f   27430  2694   rtlcarry_12_8_ins       rtlcarry_12_8
# 15  n1_y      5  i->f    28738  1308   not_rtlcarry_12_8_ins   not_rtlcarry_12_8 
# 16  no3_y     1  i0->f   29642   904   no3_y_ins               no3_y_sig
# 17  xr2_y     1  i1->t   30602   960   xr2_y_101_ins           xr2_y_101_sig
# 18  xr2_y     1  i1->t   31548   946   xr2_y_100_ins           xr2_y_100_sig
# 19  nxr2_y    1  i1->f   32343   795   nxr2_y_12_ins           nxr2_y_12_sig
# 20  na2_y     1  i0->f   32852   509   na2_y_7_ins             na2_y_7_sig
# 21  mx2_y     2  i1->t   34210  1358   rtlcarry_0_10_ins       rtlcarry_0_10
# 22  mx2_y     2  i1->t   35567  1357   rtlcarry_0_11_ins       rtlcarry_0_11
# 23  mx2_y     2  i1->t   36933  1366   rtlcarry_0_12_ins       rtlcarry_0_12
# 24  a2p_y     2  i1->t   37902   969   rtlcarry_0_13_ins       rtlcarry_0_13
# 25  a2p_y     2  i1->t   38866   964   rtlcarry_0_14_ins       rtlcarry_0_14
# 26  xr2_y     1  i1->t   39827   961   xr2_y_320_ins           xr2_y_320_sig
# 27  xr2_y     0  i1->t   41234  1407   r_14_ins                r(14)
#     r 14
#
# 1st critical path is r 14 at 41234
# 2nd critical path is r 15 at 41155

 
Spreadsheet calculation for the noa4p_y timing. noa4p_y spreadsheet timing

 
noa4p_y.vbe copied from noa4_y.vbe and edited.

ENTITY noa4p_y IS
  GENERIC (
    CONSTANT area        : NATURAL := 2268;
    CONSTANT transistors : NATURAL := 12;
    CONSTANT cin_i3      : NATURAL := 105;
    CONSTANT cin_i2      : NATURAL := 76;
    CONSTANT cin_i1      : NATURAL := 76;
    CONSTANT cin_i0      : NATURAL := 76;
    CONSTANT tplh_i3_f   : NATURAL := 380;
    CONSTANT rup_i3_f    : NATURAL := 1300;
    CONSTANT tphl_i3_f   : NATURAL := 250;
    CONSTANT rdown_i3_f  : NATURAL := 1240;
    CONSTANT tplh_i0_f   : NATURAL := 1532;
    CONSTANT rup_i0_f    : NATURAL := 1300;
    CONSTANT tphl_i0_f   : NATURAL := 1444;
    CONSTANT rdown_i0_f  : NATURAL := 1240;
    CONSTANT tplh_i1_f   : NATURAL := 1673;
    CONSTANT rup_i1_f    : NATURAL := 1300;
    CONSTANT tphl_i1_f   : NATURAL := 1303;
    CONSTANT rdown_i1_f  : NATURAL := 1240;
    CONSTANT tplh_i2_f   : NATURAL := 1706;
    CONSTANT rup_i2_f    : NATURAL := 1300;
    CONSTANT tphl_i2_f   : NATURAL := 1148;
    CONSTANT rdown_i2_f  : NATURAL := 1240
  );
  PORT (
  i0  : in BIT;
  i1  : in BIT;
  i2  : in BIT;
  i3  : in BIT;
  f   : out BIT;
  vdd : in BIT;
  vss : in BIT
  );
END noa4p_y;
ARCHITECTURE VBE OF noa4p_y IS
BEGIN
  ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on noa4p_y"
  SEVERITY WARNING;
  f <= (((i0 or i1) or i2) nand i3) after 1000ps; 
END;