A design methodology has been presented for the use of the open source Alliance synthesis software BOOM, BOOG and LOON. The objective is to use these programs to generate the fastest standard cell netlist from a VHDL behavioural description.

The tasks involved in setting up the synthesis methodology are listed below. A design flow which generates the fastest netlist for the Alliance multi8 example in the sclib is shown on the right.


Macros are cells connected together either to create a new function or to make a higher drive version. BOOG and LOON cannot infer these, so they have to be created manually by the designer.

sclib cgi2 cell For a good quality netlist from BOOG, the cells it sees should include an inverting carry cell.


BOOG and LOON have optimisation levels from 0-4 which afect the generated netlist. The default value is 2, but using different values can make the netlist faster. For BOOG in particular, using an opt level of 4 gives a faster netlist.


The full netlist delay is considered by assigning a realistic load cap and an input resistance similar in value to a gate which might be driving the input. The input resistances and output capacitances are entered into a LAX file with a defined naming scheme:

where xxxx is the input resistance in ohms; yyy the output load in fF; z the opt level.


Industry practice is to include an estimate of the wiring capacitance in the circuit delays. A simple estimate is made by adding a fixed capacitance to every input pin. This is done by editing and copying the logic descriptions to separate directories. The library without any wiring estimate is called the 0fF wireload, and a 45fF one has been added.


Fanin reduction is achieved by increasing the input resistance on non-critical inputs to bring their delays up to the critical path. Script find_rin has been written to find the correct value to use.


After the initial BOOM synthesis as above, BOOM is repeatedly run with the no optimize algorithm (-n) until there is no more improvement.

1 $ boom -VAP multi8_vasy multi8_o
2 $ boom -Vn multi8_o multi8
3 $ boom -Vn multi8 multi8_o
4 $ boom -Vn multi8_o multi8


BOOG uses one of four libraries containing only the minimum drive strength for each function, and one only of the available inverters from x1 to x8 drive.

BOOG gives the fastest netlist with 0fF wireloads; a zero input resistance; does not consider the load; and with opt level 4. The best inverter drive varies.

5 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_0_min_x4
6 $ boog -l loon_0000_300_4 multi8 multi8_o


LOON is run with the 45fF wireload library in order to optimise the timing with the estimated wire cap.

The regular LOON command is replaced by a script loop_buf_loon which

7 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_45_min_x4
8 $ rin=$(./find_rin -l loon_1500_300_0 multi8_o 2>/dev/null)
9 $ echo "rin "$rin > .buf_loon
10 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_45
11 $ ./loop_buf_loon -l loon_1500_300_4 multi8_o multi8

If the input netlist already has an acceptable fanin, then events 7-9 can be omitted.

BOOM simplifies a VHDL behavioural logic description to the constructs which BOOG can handle. BOOG converts the behavioural VHDL into a structural VHDL based upon a standard cell library. LOON optimises a structural VHDL for area and/or delay.

These programs work in sequence

A practical sequence which uses the tasks listed on the left, starting with a netlist produced by VASY and looping through all the possible BOOG netlists is

1 $ boom -VAP multi8_vasy multi8_o
2 $ boom -Vn multi8_o multi8
3 $ boom -Vn multi8 multi8_o
4 $ boom -Vn multi8_o multi8
5 $ for lib in x1 x2 x4 x8; do
6 $ for opt1 in 0 1 2 4; do
7 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_0_min_${lib}
8 $ boog -l loon_0000_300_${opt1} multi8 multi8_${opt1}
9 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_45_min_${lib}
10 $ rin=$(./find_rin -l loon_1500_300_0 multi8_${opt1})
11 $ echo "rin "$rin > .buf_loon
12 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_45
13 $ ./loop_buf_loon -l loon_1500_300_4 multi8_${opt1} multi8
14 $ done
15 $ done

The VHDL description is expanded to the VHDL subset accepted by Alliance (event 1). BOOM optimisation (events 2-4) leads to a smaller and faster netlist. BOOG is looped through four libraries containing minimum drive strength cells and one drive strength inverter (event 5) and through the four optimisation levels (event 6).

The BOOG library is defined (event 7) and BOOG is run (event 8). The input resistance needed to reduce the fanin is calculated (event 10) using the same library as BOOG but with the same wireload as LOON (event 9).

The LOON synthesis library is the complete library with a 45fF wireload (event 12). LOON is run inside the script loop_buf_loon which reduces fanin (using the value of rin written in event 11) and writes the fastest netlist to multi8.vst (event 13).