From the analysis on NAND and NOR gates, we can extend the equation for logical effort to the case of an arbitrary number of series N and P transistors. A table of logical effort for all combinations of inverting complex gates from 1-4 series transistors can be drawn up using Ohm's law and µ=2, as in Logical Effort.

This can be compared with a table of logical effort used for the vsclib design. The derivation of the numbers in this table is shown below.

Selecting the P:N Transistor Ratio for Complex Gates

In order to calculate the falling logical effort, the N transistors are sized so that the conductivity of the series transistors is the same as a single N transistor with a width of 1. For a complex gate with P:N transistor ratio of γ this means that the equivalent inverter has a drive of (P=γ,N=1), and the complex gate has (P=K_P·γ,N=K_N). Then the falling logical effort is
g_d = (K_N+K_P·γ)/(1+µ)
For the rising logical effort, we scale the P transistor of the equivalent inverter to P=µ. The N transistor is then scaled by a factor of µ/γ from this. The series P transistor of the complex gate is then K_P× bigger than the equivalent inverter, and the series N transistor is K_N× bigger. This gives a rising logical effort of
g_u = (K_P·µ+K_N·µ/γ)/(1+µ)
The logical effort g is then:
g = ½×(K_P·γ+K_N+K_P·µ+K_N·µ/γ)/(1+µ)

This is quite a useful result, as it is generic and applies as well to inverters, NAND and NOR gates.

The fastest gates can be found when
dg/dγ = 0 = K_P-K_N·µ/γ²
from which γ = √(K_N·µ/K_P) for the fastest gates.

We use this expression to draw up a table of the γ values for the fastest gates for all gates with up to 4 series P or N transistors. Our design policy is to have a lower value of γ=2 and an upper value of γ=2.5 in order to keep the output rise and fall drive strengths reasonably balanced. From this table, we can see that all gate types will have γ=2 except for the 3-NAND and 4-NAND, which as we have already seen, will use values of γ=2.33 and γ=2.5.

Now for each gate type, we have values of P:N transistor ratio (γ), P and N transistor conductivity coefficients (K_P,K_N), and a value for mobility µ=2.25. Thus for each gate type we can calculate the logical effort
g = ½×(K_P·γ+K_N+K_P·µ+K_N·µ/γ)/(1+µ).
This gives us the table at the top of the page, showing logical effort for all 16 inverting gate types with 1-4 series transistors.