nd2ab standard cell family
2-I/P OR gate
The nd2ab gates are 2-OR gates made up as 2 inverters driving a NAND gate. According to the theory of logical effort, this combination should be faster than a regular or2 gate, and it is. The speed can be compared to the or2 gates, especially the or2v0x1 which has the same output P-transistor size as the nd2abv0x1. The nd2ab gates are bigger and consume more power than the or2 gates.
z:(a+b)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nd2abv0x1
56
3.08
1.12
24.4
3.2f
69
3.31
80
2.47
nd2abv0x2
56
3.08
1.41
30.0
3.6f
72
2.48
80
1.84
nd2abv0x3
70
3.85
2.33
49.6
5.1f
76
1.35
85
1.03
nd2abv0x1
nd2abv0x2
nd2abv0x3