iv1 standard cell family

 inverter
iv1 symbol
There are five inverters with drive strengths from x2 to x12 and a P:N ratio of 1.4. There are also additional layout variants v6 and v7. The effort tables show the effort relative to the reference inverter in the vsclib, the iv1v2x2, which has a P:N ratio of 2.25.
z:a' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
rgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
iv1v0x2 1.3  32 1.76  0.55   8.4  5.4f  41  2.11  31  1.14
iv1v6x2 1.3  32 1.76  0.55   8.1  5.5f  40  2.11  31  1.14
iv1v0x4 1.3  32 1.76 1.11  16.2 10.6f  40  1.06  30  0.57
iv1v6x4 1.3  32 1.76 1.11  14.9 10.6f  39  1.06  30  0.57
iv1v7x4 1.3  32 1.76 1.11  14.8 10.4f  39  1.06  30  0.57
iv1v0x6 2.7  64 3.52 1.66  22.8 15.8f  39  0.70  30  0.38
iv1v0x8 2.7  64 3.52 2.22  29.5 20.9f  39  0.53  30  0.28
iv1v0x12 4.0  96 5.28 3.33  44.4 31.4f  39  0.35  30  0.19
iv1v0x2
 
Effort
FO4 Log.
a /\ 1.02 1.03
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iv1v0x2 schematic iv1v0x2 standard cell layout
iv1v6x2
 
Effort
FO4 Log.
a /\ 1.02 1.05
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iv1v6x2 schematic iv1v6x2 standard cell layout
iv1v0x4
 
Effort
FO4 Log.
a /\ 1.00 1.01
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iv1v0x4 schematic iv1v0x4 standard cell layout
iv1v6x4
 
Effort
FO4 Log.
a /\ 0.99 1.01
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iv1v6x4 schematic iv1v6x4 standard cell layout
iv1v7x4
 
Effort
FO4 Log.
a /\ 0.98 0.99
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iv1v7x4 schematic iv1v7x4 standard cell layout
iv1v0x6
 
Effort
FO4 Log.
a /\ 0.99 1.00
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iv1v0x6 schematic iv1v0x6 standard cell layout
iv1v0x8
 
Effort
FO4 Log.
a /\ 0.98 0.99
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iv1v0x8 schematic iv1v0x8 standard cell layout
iv1v0x12
 
Effort
FO4 Log.
a /\ 0.98 0.99
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iv1v0x12 schematic iv1v0x12 standard cell layout
Web data book for the rgalib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008