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rgalib standard cell library | |
Viewable GIF files for the vgalib. This release contains 23 inverting and non-inverting gates. Each cell has a typical timing arc and input pin capacitance in 0.13µm generic technology, along with its leakage and dynamic power, size, layout, and the transistor schematic. Transistor sizes are given in lambda, where for this 0.13µm technology, lambda=0.055µm. The cell height is 88 lambda (4.84µm) with power supply rails 8 lambda (0.66µm) wide in metal-2. The maximum P and N transistor widths before folding are 28λ and 20λ respectively.
This is a gate array library where each P and N transistor pair shares the same poly. It is similar to one from Virage Logic, although the architecture is also used elsewhere.
description of the rgalib characterisation methodology (same as the vsclib)
aoi21 standard cell family, rgalib
1× 2/1 AND-NOR gates
iv1 standard cell family, rgalib
8× inverters
mxi2 standard cell family, rgalib
1× inverting 2-way muxes
nd2 standard cell family, rgalib
4× 2-NAND gates
nd2a standard cell family, rgalib
1× 2-NAND gates with one inverting input
nd3 standard cell family, rgalib
1× 3-NAND gates
nr2 standard cell family, rgalib
2× 2-NOR gates
nr2a standard cell family, rgalib
1× 2-NOR gates with one inverting input
nr3 standard cell family, rgalib
1× 3-NOR gates
oai21 standard cell family, rgalib
1× 2/1 OR-NAND gates
xnr2 standard cell family, rgalib
1× 2 input exclusive NOR gates
xor2 standard cell family, rgalib
1× 2 input exclusive OR gates