oan21b standard cell family

 2-OR into 2-AND gate, inverted input
oan21b symbol
Minimum drive cell with a P/N ratio of about 2. The function is made from 2 2-I/P NOR gates with a stage gain of about 1.7.
z:((a1+a2)*b') cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oan21bv0x05 2.3  56 3.08  0.74  17.6  3.1f  92  5.82 109  3.92
oan21bv0x05
 
Effort
FO4 Log.
a1 /\
¯_ 2.51
a2 /\
¯_ 2.31
b /\ 1.43 1.65
¯_
oan21bv0x05 schematic oan21bv0x05 standard cell layout
Web data book for the wsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008