xor3 standard cell family

3-I/P exclusive OR gate
xor3 symbol
The v0 version is a 1 or 2 stage gate. The v1 versions are 2 to 4 stage gates from the a and b inputs; 1 or 2 stages from the c input. Although the v1 versions have more stages, their performance is better. The v0 version is included only as a comparison, since the large internal parasitic capacitances and 3 P-transistors in series make the gate slow. The xor3v1x05 is made from 2 xor2v0x05 cells; the xor3v1x1 from 2 xor2v0x1 cells; the xor3v1x2 from an xor2v0x1 and xor2v0x2.
z:(a^b^c) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xor3v0x05 7.0 168 9.24 2.33  52.1  9.3f 157  4.84 136  3.50
xor3v1x05 5.0 120 6.60 1.36  36.7  4.4f 148  6.17 148  4.76
xor3v1x1 5.3 128 7.04 2.15  55.7  6.1f 145  3.51 144  2.59
xor3v1x2 7.0 168 9.24 3.20  85.0  6.0f 160  1.82 161  1.34
xor3v0x05
 
Effort
FO4 Log.
a /\ 4.02 4.21
¯_ 4.38
b /\ 3.29 3.47
¯_ 5.34
c /\ 4.25 6.42
¯_ 4.26
xor3v0x05 schematic xor3v0x05 standard cell layout
xor3v1x05
 
Effort
FO4 Log.
a /\ 3.36 2.26
¯_ 3.36
b /\ 3.52 2.83
¯_ 3.52
c /\ 2.07 2.46
¯_ 2.12
xor3v1x05 schematic xor3v1x05 standard cell layout
xor3v1x1
 
Effort
FO4 Log.
a /\ 3.07 1.78
¯_ 3.08
b /\ 3.13 2.16
¯_ 3.13
c /\ 1.93 2.29
¯_ 1.93
xor3v1x1 schematic xor3v1x1 standard cell layout
xor3v1x2
 
Effort
FO4 Log.
a /\ 2.89 0.92
¯_ 2.89
b /\ 2.85 1.10
¯_ 2.85
c /\ 1.91 2.25
¯_ 1.90
xor3v1x2 schematic xor3v1x2 standard cell layout