| vlsitechnology.org /detff/divide by 3 | |
Symmetrical Divide by 3 Using DETFF | |
This article describes the design of a symmetrical divide by 3 circuit which uses dual edge triggered flip-flops (DETFF).
A DETFF switches on both clock edges. This means that a divide by 3 using a normal FF becomes a divide by 6 using a DETFF.
A DETFF is made from two latches in parallel, one of them transparent when the clock is high and one when it is low. The latch outputs are muxed to the flop output on opposite phases of the clock.
The divide by 6 counter is three DETFFs with the inverted output of the last fed back to the input of the first. In the schematic below, each DETFF is made up of two parallel latches and an output mux.
A Spice deck has been coded and simulated to check the output waveforms. It can be found in the support files tab on the left. The output waveforms from a winspice run are shown below.
The main clock is running at 1GHz, and the three DETFF ouputs are symmetrical 333MHz clocks. The process technology is a generic 0.13um under typical conditions.