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XOR3 cell made with single inverting gate

  
gate count               1400
number of cells           562
number of library cells   104
number of used cells       38
max fanin                  17
max input capacitance     188
max internal fanout        34
critical path  0fF       2302
critical path  6fF       2931
   xor3 xor3 symbol

Frequently the XOR gates are grouped together so that two of them could be replaced by a single 3-input XOR gate. The advantages of this are:

ex16_1 example

In this experiment a single stage 3-XOR gate has been added to the library. This type of gate is slow compared to making a gate from two regular 2-XOR gates. The Prop delay is similar, but the Ramp delay is about twice for the same value of input capacitance. In addition, a 3-XOR made from two 2-XOR gates has one input with a faster input passing only through the final gate. The physical size is nearly 50% larger than two separate 2-XOR gates. The schematic used is shown below.

xor3v0x05 schematic

It is theoretically possible to minimise the number of transistors, but this increases the amount of internal cell connections beyond the limits of the vsclib cell height.

The 3-XOR timing in the cell used by BOOG is set to 1500ps in order to discourage the cell use except where a real advantage is seen. This is 3X the Prop delay of regular non-inverting gates. Despite this, eight of these gates are chosen, none of them being in the critical path. Three of these drive non-critical outputs and are replaced by an x2 drive strength equivalent netlist by a script, leaving five xor3v0x05 cells.

Circuit speed is slightly slower because the inputs of some of the xor3v0x05 gates load the critical path and have a higher pin capacitance than the equivalent 2-input XOR gates.

Area is more because a 3-XOR gate is bigger than two separate 2-XOR gates. The cell count has increased because there are fewer xooi21 and xoon21 cells, replaced by separate 2-NOR and 2-XOR or 2-XNOR combinations.

Table of synthesis results  
  critical path (ps) gate count cell count porosity library cells used cells
synthesis 1 4279 1561 923 43%   9  8 basic inverters, NAND & NOR gates
synthesis 2 4236 1472 792 45%  15 12 AND & OR gates
synthesis 3 4157 1357 696 46%  19 16 AOI & OAI gates, 2/1 and 2/2
synthesis 4 4157 1357 696 46%  20 16 mxi2 2-way inverting mux
synthesis 5 3983 1343 668 48%  21 16 cgi2 carry generator inverting
synthesis 6 3948 1352 668 48%  28 18 inverters with multiple drive strengths
synthesis 7 3061 1433 666 51%  70 27 x2 drive strengths for all functions
synthesis 8 3056 1456 666 52%  70 30 BOOG with x1 drive strengths
synthesis 9 2960 1476 666 53%  70 32 BOOG with x05 drive strengths
synthesis 10 2963 1480 666 53%  76 34 nd2a and nr2a cells
synthesis 11 2963 1480 666 53%  79 34 nd2ab type of 2-OR
CyHP library 3778 1539 832 46%  18 17 Minimum size library
synthesis 12 2908 1362 553 54%  91 38 AND/OR into XOR/XNOR
synthesis 13 2893 1378 551 55% 103 39 aoi211, aoi31, oai211 & oai31
synthesis 14 2931 1400 562 55% 104 38 3-XOR gate, 1/2 stage delays
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