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gate count 1390 number of cells 536 number of library cells 109 number of used cells 40 max fanin 17 max input capacitance 192 max internal fanout 34 critical path 0fF 2282 critical path 6fF 2886 |
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xor3
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xnr3
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As we have seen, frequently the XOR and XNOR gates are grouped together so that two of them could be replaced by a single 3-input XOR or XNOR gate.
Previously a single stage 3-XOR gate was tried, but proved to be slow and,
especially, large. Now 3-XOR and 3-XNOR gates are made by joining
two 2-input gates into one. The area is no more than the separate gates,
and can be less. The delay is reduced because the 6fF wireload capacitance
on the input of the second gate is no longer present.
The schematic for the xor3v1x1 below shows it is
basically made up of two xor2v0x1 cells.
The a and b inputs pass through two gates, but the c input is faster since it passes through the second gate only.
Since the 3-XOR and 3-XNOR gates are now efficient implementations of the function, the cell delay used by BOOG is set equal to the 2-AND gate at 400ps. Now 29 xor3 cells and 10 xnr3 cells are chosen by BOOG, although after replacing non-critical outputs using these gates with an equivalent netlist made up of 2-XOR and 2-XNOR gates having a lower input pin capacitance, there remain 23 xor3 and 10 xnr3 cells.
Although none of the 3-input XOR and XNOR gates appears on the critical path, four of them have been buffered up to an x1 or x2 drive strength. This implies that they can appear on the critical path, and need to be sized up to remove them. This is why, even if they are not on the critical path, their presence improves the netlist performance.
fanout -- delay--
x 1 17 192
1 aoi22v0x2 1 b1->z 279 87
2 oai21v0x2 4 a2->z 415 136
3 iv1v0x4 1 a->z 464 49
4 oai21v0x2 4 a2->z 603 139
5 iv1v0x4 1 a->z 652 49
6 oai21v0x2 4 a2->z 792 140
7 iv1v0x4 1 a->z 841 49
8 oai21v0x2 4 a2->z 980 139
9 iv1v0x4 1 a->z 1029 49
10 oai21v0x2 4 a2->z 1167 138
11 iv1v0x3 1 a->z 1222 55
12 oai21v0x2 4 a2->z 1372 150
13 iv1v0x3 1 a->z 1428 56
14 oai21v0x2 5 a2->z 1598 170
15 xoon21v0x2 1 b->z 1700 102
16 cgi2v0x2 4 c->z 1835 135
17 iv1v0x2 1 a->z 1890 55
18 nd2av0x2 1 a->z 2000 110
19 oai21v0x2 3 b->z 2125 125
20 xor2v0x2 1 b->z 2216 91
21 cgi2v0x2 2 c->z 2312 96
22 iv1v0x4 1 a->z 2361 49
23 cgi2v0x2 2 c->z 2450 89
24 an2v0x2 2 b->z 2569 119
25 an2v0x2 2 b->z 2715 146
26 xaon21v0x2 0 a1->z 2886 171
r 15 |
| Table of synthesis results | |||||||
| critical path (ps) | gate count | cell count | porosity | library cells | used cells | ||
| synthesis 1 | 4279 | 1561 | 923 | 43% | 9 | 8 | basic inverters, NAND & NOR gates |
| synthesis 2 | 4236 | 1472 | 792 | 45% | 15 | 12 | AND & OR gates |
| synthesis 3 | 4157 | 1357 | 696 | 46% | 19 | 16 | AOI & OAI gates, 2/1 and 2/2 |
| synthesis 4 | 4157 | 1357 | 696 | 46% | 20 | 16 | mxi2 2-way inverting mux |
| synthesis 5 | 3983 | 1343 | 668 | 48% | 21 | 16 | cgi2 carry generator inverting |
| synthesis 6 | 3948 | 1352 | 668 | 48% | 28 | 18 | inverters with multiple drive strengths |
| synthesis 7 | 3061 | 1433 | 666 | 51% | 70 | 27 | x2 drive strengths for all functions |
| synthesis 8 | 3056 | 1456 | 666 | 52% | 70 | 30 | BOOG with x1 drive strengths |
| synthesis 9 | 2960 | 1476 | 666 | 53% | 70 | 32 | BOOG with x05 drive strengths |
| synthesis 10 | 2963 | 1480 | 666 | 53% | 76 | 34 | nd2a and nr2a cells |
| synthesis 11 | 2963 | 1480 | 666 | 53% | 79 | 34 | nd2ab type of 2-OR |
| CyHP library | 3778 | 1539 | 832 | 46% | 18 | 17 | Minimum size library |
| synthesis 12 | 2908 | 1362 | 553 | 54% | 91 | 38 | AND/OR into XOR/XNOR |
| synthesis 13 | 2893 | 1378 | 551 | 55% | 103 | 39 | aoi211, aoi31, oai211 & oai31 |
| synthesis 14 | 2931 | 1400 | 562 | 55% | 104 | 38 | 3-XOR gate, 1/2 stage delays |
| synthesis 15 | 2886 | 1390 | 536 | 56% | 109 | 40 | 3-XOR/XNOR gates as 2×2-I/P gates |
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