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x4 Drive Strength for Critical Path Cells

   
gate count               1571
number of cells           540
number of library cells   155
number of used cells       49
max fanin                  17
max input capacitance     197
max internal fanout        34
critical path  0fF       2148
critical path  6fF       2567

An x4 drive strength is now added for all functions that are not already so big so that an x4 drive strength cell would be excessively large, much above 160λ or 20 tracks wide.

Compared to the previous experiment, where only x3 drive strength cells were available, there is a 3.7% speed improvement at the cost of a 3.8% area increase. The x3 and x4 drive strength usage is (where '-' indicates no cell in library): 

       x3   x4
an2     0    2
aoi22   1    0
cgi2   14    -
iv1     0   17
nd2a    0    1
nr2a    0    1
nr2     1    1
oai21  11   18
xaon21  2    -
xnr2    0    -
xoon21  3    -
xor2   12    1

The bulk of the x4 usage is with the oai21v0x4 cell. Usage of other cells is probably restricted because many functions are limited to an x3 drive strength by their physical size, like the cgi2v0x3. This constrains other critical path cells to a similar drive strength in order to not present an excessive input pin capacitance.

Instead of adding x4 drive strength cells, another possiblity is to use them to replace existing x3 drive strength cells. This experiment would test whether an x3 drive strength is useful if x2 and x4 drive strengths are also available. A comparison table is shown below.

Performance Comparison with Different Drive Strengths
  critical path (ps) gate count cell count library cells used cells
x2 only 2886 1390 536 109 40
x2,x3 only 2665 1514 538 136 46
x2,x4 only 2573 1554 537 136 48
x2,x3,x4 2567 1571 540 155 49

By adding x3 drive strengths to an existing library of x2 and x4 drive strength cells, the speed is improved by 0.2%. This isn't much, so the decision on including x3 drive strength cells is very much one of making the tradeoff between library design effort and ultimate desired performance.

The critical path shows extensive use of x4 drive strength cells where they exist. 

    x 1          17                  197
 1  nd4v0x2       1  d->z      295    98
 2  oai21v0x4     4  b->z      390    95
 3  iv1v0x6       1  a->z      440    50
 4  oai21v0x4     4  a2->z     547   107
 5  iv1v0x6       1  a->z      597    50
 6  oai21v0x4     4  a2->z     711   114
 7  iv1v0x6       1  a->z      761    50
 8  oai21v0x4     4  a2->z     874   113
 9  iv1v0x6       1  a->z      924    50
10  oai21v0x4     4  a2->z    1042   118
11  iv1v0x6       1  a->z     1092    50
12  oai21v0x4     4  a2->z    1198   106
13  xor2v0x2      1  b->z     1317   119
14  cgi2v0x3      3  b->z     1434   117
15  iv1v0x4       1  a->z     1488    54
16  cgi2v0x3      4  c->z     1604   116
17  iv1v0x3       1  a->z     1654    50
18  nd2av0x4      1  a->z     1762   108
19  oai21v0x4     3  b->z     1854    92
20  xor2v0x3      1  b->z     1939    85
21  cgi2v0x3      2  c->z     2032    93
22  iv1v0x4       1  a->z     2086    54
23  cgi2v0x3      2  c->z     2162    76
24  an2v0x4       2  b->z     2274   112
25  an2v0x4       2  b->z     2401   127
26  xaon21v0x3    0  a2->z    2537   136
    r 15

Table of synthesis results  
  critical path (ps) gate count cell count porosity library cells used cells
synthesis 1 4279 1561 923 43%   9  8 basic inverters, NAND & NOR gates
synthesis 2 4236 1472 792 45%  15 12 AND & OR gates
synthesis 3 4157 1357 696 46%  19 16 AOI & OAI gates, 2/1 and 2/2
synthesis 4 4157 1357 696 46%  20 16 mxi2 2-way inverting mux
synthesis 5 3983 1343 668 48%  21 16 cgi2 carry generator inverting
synthesis 6 3948 1352 668 48%  28 18 inverters with multiple drive strengths
synthesis 7 3061 1433 666 51%  70 27 x2 drive strengths for all functions
synthesis 8 3056 1456 666 52%  70 30 BOOG with x1 drive strengths
synthesis 9 2960 1476 666 53%  70 32 BOOG with x05 drive strengths
synthesis 10 2963 1480 666 53%  76 34 nd2a and nr2a cells
synthesis 11 2963 1480 666 53%  79 34 nd2ab type of 2-OR
CyHP library 3778 1539 832 46%  18 17 Minimum size library
synthesis 12 2908 1362 553 54%  91 38 AND/OR into XOR/XNOR
synthesis 13 2893 1378 551 55% 103 39 aoi211, aoi31, oai211 & oai31
synthesis 14 2931 1400 562 55% 104 38 3-XOR gate, 1/2 stage delays
synthesis 15 2886 1390 536 56% 109 40 3-XOR/XNOR gates as 2×2-I/P gates
synthesis 16 2665 1514 538 60% 136 46 x3 drive strength cells
synthesis 17 2567 1571 540 61% 155 49 x4 drive strength cells
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