Non-inverting Buffers

gate count               1628
number of cells           541
number of library cells   188
number of used cells       55
max fanin                  17
max input capacitance     214
max internal fanout        34
critical path  0fF       2103
critical path  6fF       2493

In this experiment a set of non-inverting buffers is added to the library. These are the drive strengths x05,x1,x2,x3,x4, x6,x8,x12, plus a special buffer, the bf1v4x1 which uses a first inverter with minimum transistor sizes and input capacitance.

bf1v0x1 schematic	bf1v4x1 schematic

There are two principal ways in which the buffers can improve the critical path.

• The buffer is inserted between a net on the critical path and gates which drive non-critical outputs. In this case, we expect the bf1v4x1 buffer to be used because it has the lowest input capacitance and loads the critical path least.
• Buffers are inserted on heavily loaded input pins because the buffer delay is less than the input delay. The input delay here is calculated assuming the cell driving the input has a drive strength of 1ps/fF (=1kΩ), and the delay is the product of this drive strength and the input capacitance. Consider for example, pin x1 which has an input capacitance of 214fF being buffered by a bf1v0x12 buffer, shown on the right. The buffer has the characteristics below:

  CONSTANT cin_a : NATURAL := 17; CONSTANT rdown_a_z : NATURAL := 290; CONSTANT rup_a_z : NATURAL := 370; CONSTANT tpll_a_z : NATURAL := 89; CONSTANT tphh_a_z : NATURAL := 73;

  - the unbuffered input delay is 1 × 214 = 214ps
  - the buffered input delay is 1 × 17 = 17ps
  - the buffer rise delay is 73 + 0.37 × 214 = 152ps
  - the buffer fall delay is 89 + 0.29 × 214 = 151ps
  - the average buffer delay is 152ps

  So the average total buffered input delay is 17 + 151 = 168ps, which is less than 214ps without the buffer.

LOON has five optimisation levels, from 0-4. At levels 0 and 1, decoupling buffers are never inserted. At levels 2-4, decoupling buffers will be inserted if LOON calculates that they improve the critical path speed. The problem is that optimisation level 4 is the one which most favours speed over area, but there is no user control over whether decoupling buffers are inserted or not. In a synthesis flow which successively optimises the netlist with LOON, one can easily find that decoupling buffers are inserted too soon into the netlist.

It is better in fact to optimise the netlist without any inserted buffers, and then see whether further optimisations with buffers give any speed improvement. The optimised netlist is the one from the previous experiment, and using LOON with buffers in the library, the critical path can be reduced by 0.2% at the cost of a 0.2% area increase and three inserted buffers.

If instead the LOON optimisation starts with a library containing buffers, the final critical path is actually slower by 0.6%, although the area is reduced by 1.8%.

The result of this is the need to supply five synthesis libraries for the Alliance synthesis flow.

1. A library with only the weakest drive strength for each function and idealised timing for BOOG
2. A regular library as characterised but with no buffers
3. As above but with 6fF added to the input pin capacitance to model a wireload
4. The full regular library including buffers
5. As above with 6fF added to the input pin capacitances

alliance/vbe

vsclib013_b
vsclib013_nobuf
vsclib013_6_nobuf
vsclib013
vsclib013_6

Buffer insertion on the inputs can be problematic with LOON and will be handled in a special way in the next experiment.