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Synthesis with Current vsclib Library

   
gate count               1695
number of cells           560
number of library cells   188
number of used cells       58
max fanin                   4
max input capacitance      94
max internal fanout        34
critical path  0fF       2123
critical path  6fF       2439

The vsclib has 209 cells. These include most of the ones included previously plus some new functions and variants of existing functions. The variants are for example different forms of 2-input XOR gates and inverters with different P/N transistor ratios. This experiment uses the flow developed and the current library in order to compare its performance.

The ctitical path delay is practically the same, 0.08% faster, but the area is significantly less, down 3.6%. Later experiments will continue this investigation.

Table of synthesis results  
  critical path (ps) gate count cell count porosity library cells used cells
synthesis 1 4279 1561 923 43%   9  8 basic inverters, NAND & NOR gates
synthesis 2 4236 1472 792 45%  15 12 AND & OR gates
synthesis 3 4157 1357 696 46%  19 16 AOI & OAI gates, 2/1 and 2/2
synthesis 4 4157 1357 696 46%  20 16 mxi2 2-way inverting mux
synthesis 5 3983 1343 668 48%  21 16 cgi2 carry generator inverting
synthesis 6 3948 1352 668 48%  28 18 inverters with multiple drive strengths
synthesis 7 3061 1433 666 51%  70 27 x2 drive strengths for all functions
synthesis 8 3056 1456 666 52%  70 30 BOOG with x1 drive strengths
synthesis 9 2960 1476 666 53%  70 32 BOOG with x05 drive strengths
synthesis 10 2963 1480 666 53%  76 34 nd2a and nr2a cells
synthesis 11 2963 1480 666 53%  79 34 nd2ab type of 2-OR
CyHP library 3778 1539 832 46%  18 17 Minimum size library
synthesis 12 2908 1362 553 54%  91 38 AND/OR into XOR/XNOR
synthesis 13 2893 1378 551 55% 103 39 aoi211, aoi31, oai211 & oai31
synthesis 14 2931 1400 562 55% 104 38 3-XOR gate, 1/2 stage delays
synthesis 15 2886 1390 536 56% 109 40 3-XOR/XNOR gates as 2×2-I/P gates
synthesis 16 2665 1514 538 60% 136 46 x3 drive strength cells
synthesis 17 2567 1571 540 61% 155 49 x4 drive strength cells
synthesis 18 2523 1611 540 62% 167 49 x6 drive strength cells
synthesis 19 2497 1625 538 62% 179 54 x8 drive strength cells
synthesis 20 2493 1628 541 62% 188 55 buffers to decouple non-critical paths
synthesis 21 2441 1758 563 64% 188 55 input buffers
synthesis 22 2550 1717 535 64% 188 55 optimised Alliance flow
synthesis 23 2439 1695 560 63% 188 58 current 209 cell vsclib
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