Basic Non-Inverting Gates - an2, an3, an4, or2, or3, or4

gate count               1472
number of cells           792
number of library cells    15
number of used cells       12
max fanin                  17
max input capacitance     194
max internal fanout        40
critical path  0fF       2922
critical path  6fF       4236

The addition of these cells can improve both the speed and the density of the circuit. In the literature though (e.g. www.aime-toulouse.fr/~noullet/publis/racl.pdf), it is reported that these cells do nothing for circuit speed and density.

Articles like this probably reach their conclusions because they fail to use any wiring capacitance during synthesis. This means that a 2-NAND and INV combination is the same as a single 2-AND gate, allowing the 2-AND gate to be removed from the library. If instead a statistical wiring capacitance, or wireload, is used for the 2-NAND output, then the 2-AND will be quicker because it avoids the delays caused by driving this extra capacitance.

This can be seen in this synthesis using the Alliance software. Using the 6fF wireload, (ie. there is 6fF of estimated wire capacitance for every fanout), the use of the non-inverting gates improves the speed by 1.0%. But using a 0fF wireload, the critical path is slower by 0.4%.

The selection process used by BOOG to choose the non-inverting gates is very dependent on the cell delays which it sees.
If the Prop delay is too small, then the non-inverting gates are preferentially selected over the inverting gates, and the resulting netlist has poorer performance. To produce the result here, in the library used by BOOG:

the inverting gates' Prop delay has been set to 50ps;
AND-type non-inverting gates' Prop delay has been set to 400ps;
OR-type non-inverting gates' Prop delay has been set to 500ps;
and the XOR and XNOR gates' Prop delay has been set to 75ps.

The very high Prop delay of the non-inverting gates should cause BOOG not to choose them. But they are chosen, even if they cause the delay seen by BOOG to increase (from 5205 to 5948). The mix between inverting and non-inverting gates seems about right, but it is quite possible that a different value for the non-inverting gates' Prop delay would improve the overall timing.

The critical path delay using this set of cells is shown below.

               fanout         -- delay--
    y 1          10                  109
 1  iv1v0x2      33  a->z      779   670
 2  nr2v0x1       1  b->z      869    90
 3  xor2v0x1      1  b->z      976   107
 4  xnr2v0x1      1  b->z     1078   102
 5  nd2v0x2       1  a->z     1143    65
 6  nd2v0x2       1  a->z     1207    64
 7  nd2v0x2       4  a->z     1347   140
 8  nr2v0x1       1  b->z     1429    82
 9  or2v0x2       1  b->z     1541   112
10  nd2v0x2       4  a->z     1685   144
11  nd2v0x2       1  a->z     1750    65
12  nd3v0x1       4  c->z     1922   172
13  nd2v0x2       1  a->z     1987    65
14  nd3v0x1       4  c->z     2159   172
15  nd2v0x2       1  a->z     2223    64
16  nd3v0x1       4  c->z     2395   172
17  nd2v0x2       1  a->z     2460    65
18  nd3v0x1       4  c->z     2632   172
19  nd2v0x2       1  a->z     2697    65
20  nd3v0x1       3  c->z     2841   144
21  iv1v0x2       2  a->z     2920    79
22  nd2v0x2       1  b->z     2983    63
23  nd2v0x2       1  a->z     3048    65
24  nd2v0x2       3  a->z     3168   120
25  xor2v0x1      2  b->z     3299   131
26  nd2v0x2       1  a->z     3363    64
27  nd3v0x1       3  c->z     3512   149
28  nd2v0x2       1  a->z     3577    65
29  nd3v0x1       2  c->z     3691   114
30  an2v0x2       2  b->z     3820   129
31  an2v0x2       2  b->z     3947   127
32  nd2v0x2       1  b->z     4017    70
33  xnr2v0x1      0  b->z     4236   219
    r 15