nd4 standard cell family

 4-I/P NAND gate
nd4 symbol
4 cells with their P/N ratio set to 2.5, close to the P/N ratio of 2.6 which gives the fastest speed, as well as balanced rise and fall drive strengths.
z:(a*b*c*d)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd4v0x05 2.3  56 3.08  0.60   6.8  2.6f  57  5.95  43  5.43
nd4v0x1 2.3  56 3.08 1.02  10.3  4.1f  54  3.50  41  3.26
nd4v0x2 3.3  80 4.40 1.50  14.3  6.1f  52  2.38  39  2.17
nd4v0x3 4.0  96 5.28 1.18  18.6  7.5f  53  1.86  39  1.72
nd4v0x05
 
Effort
FO4 Log.
a /\ 1.87 1.78
¯_
b /\ 1.86 1.89
¯_
c /\ 1.75 1.88
¯_
d /\ 1.57 1.74
¯_
nd4v0x05 schematic nd4v0x05 standard cell layout
nd4v0x1
 
Effort
FO4 Log.
a /\ 1.77 1.67
¯_
b /\ 1.74 1.73
¯_
c /\ 1.62 1.69
¯_
d /\ 1.48 1.62
¯_
nd4v0x1 schematic nd4v0x1 standard cell layout
nd4v0x2
 
Effort
FO4 Log.
a /\ 1.81 1.76
¯_
b /\ 1.75 1.78
¯_
c /\ 1.60 1.70
¯_
d /\ 1.45 1.61
¯_
nd4v0x2 schematic nd4v0x2 standard cell layout
nd4v0x3
 
Effort
FO4 Log.
a /\ 1.79 1.74
¯_
b /\ 1.76 1.80
¯_
c /\ 1.60 1.67
¯_
d /\ 1.43 1.57
¯_
nd4v0x3 schematic nd4v0x3 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008