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vsclib standard cell library | |
Viewable GIF files for the vsclib. This release contains 319 inverting and non-inverting gates, 1 flip-flop and 2 latches. Each cell has a typical timing arc and input pin capacitance in 0.13µm generic technology, along with its leakage and dynamic power, size, layout, and the transistor schematic. Transistor sizes are given in lambda, where for this 0.13µm technology, lambda=0.055µm. The cell height is 72 lambda (3.96µm) with power supply rails 8 lambda (0.44µm) wide. The maximum P and N transistor widths before folding are 28λ and 20λ respectively.
vsclib standard cell physical layout description
description of the vsclib characterisation methodology
an2 standard cell family, vsclib
12× 2-AND gates
an3 standard cell family, vsclib
7× 3-AND gates
an4 standard cell family, vsclib
5× 4-AND gates
aoi112 standard cell family, vsclib
1× 1/1/2 AND-NOR gates
aoi21 standard cell family, vsclib
3× 2/1 AND-NOR gates
aoi21a2 standard cell family, vsclib
1× 2/1 AND-NOR gates with inverted input
aoi21a2b standard cell family, vsclib
2× 2/1 AND-NOR gates with two inverted inputs
aoi21b standard cell family, vsclib
1× 2/1 AND-NOR gates with inverted input
aoi211 standard cell family, vsclib
4× 2/1/1 AND-NOR gates
aoi22 standard cell family, vsclib
6× 2/2 AND-NOR gates
aoi31 standard cell family, vsclib
4× 3/1 AND-NOR gates
aon21 standard cell family, vsclib
1× 2/1 AND-OR gates
aon21b standard cell family, vsclib
5× 2/1 AND-OR gates with inverted input
bf1 standard cell family, vsclib
22× non-inverting buffers
bsi2 standard cell family, vsclib
1× 2-bit barrel shifters
cgi2 standard cell family, vsclib
4× carry generator inverting gates
cgi2ab standard cell family, vsclib
3× carry generator inverting gates with a,b pins non-inverting
cgi2b standard cell family, vsclib
4× carry generator inverting gates with b pin non-inverting
cgi2c standard cell family, vsclib
4× carry generator inverting gates with c pin non-inverting
dfnt1 standard cell family, vsclib
1× positive edge clock flip-flop with Q output
dly1 standard cell family, vsclib
1× delay cells made from 4 small inverters
dly2 standard cell family, vsclib
2× delay cells made from 2 slow inverters
ha2 standard cell family, vsclib
1× 2-bit half adder gates
iv1 standard cell family, vsclib
35× inverters
lant1 standard cell family, vsclib
2× active high enable latch
mxi2 standard cell family, vsclib
8× inverting 2-way muxes
mxn2 standard cell family, vsclib
3× non-inverting 2-way muxes
nd2 standard cell family, vsclib
26× 2-NAND gates
nd2a standard cell family, vsclib
7× 2-NAND gates with one inverting input
nd2ab standard cell family, vsclib
5× 2-OR gates (faster and larger version using inverters and 2-NAND)
nd3 standard cell family, vsclib
11× 3-NAND gates
nd3a standard cell family, vsclib
1× 3-NAND gates with one inverted input
nd3ab standard cell family, vsclib
1× 3-NAND gates with two inverted inputs
nd4 standard cell family, vsclib
4× 4-NAND gates
nr2 standard cell family, vsclib
14× 2-NOR gates
nr2a standard cell family, vsclib
6× 2-NOR gates with one inverting input
nr3 standard cell family, vsclib
6× 3-NOR gates
nr3a standard cell family, vsclib
1× 3-NOR gates with one inverted input
nr3ab standard cell family, vsclib
1× 3-NOR gates with two inverted inputs
nr4 standard cell family, vsclib
3× 4-NOR gates
oai21 standard cell family, vsclib
7× 2/1 OR-NAND gates
oai21a2 standard cell family, vsclib
2× 2/1 OR-NAND gates with one inverted input
oai21a2b standard cell family, vsclib
1× 2/1 OR-NAND gates with two inverted inputs
oai21b standard cell family, vsclib
1× 2/1 OR-NAND gates with one inverted input
oai211 standard cell family, vsclib
2× 2/1/1 OR-NAND gates
oai22 standard cell family, vsclib
3× 2/2 OR-NAND gates
oai23a standard cell family, vsclib
1× 2/3 OR-NAND gates with shared inputs
oai31 standard cell family, vsclib
3× 3/1 OR-NAND gates
oan21 standard cell family, vsclib
1× 2/1 OR-AND gates
oan21b standard cell family, vsclib
1× 2/1 OR-AND gates with one inverted input
or2 standard cell family, vsclib
8× 2-OR gates
or3 standard cell family, vsclib
7× 3-OR gates
or4 standard cell family, vsclib
6× 4-OR gates
xaoi21 standard cell family, vsclib
3× 2/1 AND into exclusive NOR gates
xaon21 standard cell family, vsclib
4× 2/1 AND into exclusive OR gates
xnai21 standard cell family, vsclib
3× 2/1 XNOR into NAND gates
xnr2 standard cell family, vsclib
7× 2 input exclusive NOR gates
xnr3 standard cell family, vsclib
3× 3 input exclusive NOR gates
xooi21 standard cell family, vsclib
3× 2/1 OR into exclusive NOR gates
xoon21 standard cell family, vsclib
4× 2/1 OR into exclusive OR gates
xor2 standard cell family, vsclib
19× 2 input exclusive OR gates
xor3 standard cell family, vsclib
4× 3 input exclusive OR gates