Syn Intro-3

Alliance Synthesis LOON

LOON reads a structural VHDL netlist and optimises it by selecting the best cell in the library for each instance. Best means the one giving the fastest critical path and the smallest area. When BOOG has been used to create the initial structural VHDL netlist, this optimisation is essential since BOOG only uses one drive strength for each logical function.

The LOON synthesis can be controlled by a LAX file. This is used to set the input resistance, the output capacitive load and the synthesis priority level, as shown below.

#M{4}
#I{
x(0):1000;
 ...
x(7):1000;
y(0):1000;
 ...
y(7):1000;
}
#C{
r(15):50;
 ...
r(0):50;
}

The M{4} line sets the priority at 4, which means 100% delay and 0% area optimisation. A priority of 0 means 100% area and 0% delay optimisation, priority 1 is 75% area and 25% delay and so forth. Priority levels 2-4 will insert buffers if these improve the critical path, while priority levels 0-1 never will. In practice, priority levels 2 and 3 give the same results, and if no buffers are inserted, the result is the same as priority level 1. Priority level 4 does not always give the fastest critical path. Generally priority level 0 gives the smallest result and level 4 gives the largest.

The lines after #I{ set an input resistance in ohms. This is used to calculate the input delay along with the input pin capacitance coming from the values in the library VBE files. This input delay is part of the critical path and is used by LOON in its optimisation.

The lines after #C{ set the output load in femtofarads. The critical path delay includes the delay of the output gate driving this load.

LOON measures the critical path using the average of the rise and fall delays for each gate.

Excerpt from a critical path	The xor2v0x2 gate has a fanout of one driving pin c of the xor3v1x2. The capacitance of pin c is 13fF. The average drive strength of the xor2v0x2 is (1.32+1.75)÷2 = 1.535. The Ramp delay is then 1.535×13 = 20ps. The average xor2v0x2 Prop delay is (35+80+61+86)÷4 = 65ps. The average xor2v0x2 delay is then Prop+Ramp = 65+20 = 85ps. Note that the drive strengths of the xor2v0x2 gate are already averaged, since the drive strength is typically different if the XOR is inverting or non-inverting. But with the simplified Alliance timing model, this difference cannot be modelled and an average value is used.
xor2v0x2 1 b->z 85 xor3v1x2 1 c->z 79
Excerpt from xor2v0x2.vbe
ENTITY xor2v0x2 IS GENERIC ( ... CONSTANT rdown_b_z : NATURAL := 1320; CONSTANT rup_b_z : NATURAL := 1750; CONSTANT tphl_b_z : NATURAL := 35; CONSTANT tplh_b_z : NATURAL := 80; CONSTANT tphh_b_z : NATURAL := 61; CONSTANT tpll_b_z : NATURAL := 86; ... z <= (b xor a) after 1000 ps; END;
Excerpt from xor3v1x2.vbe
ENTITY xor3v1x2 IS GENERIC ( ... CONSTANT cin_c : NATURAL := 13; ... z <= ((a xor b) xor c) after 1000 ps; END;

or4 netlist LOON will only change the drive strength of gates that are on the critical path. If, as a result of sizing up a gate, the critical path changes, then LOON will consider the new critical path.
LOON will not:

Change the drive strength of gates not on the critical path, such as non-critical outputs.
Buffer any inputs that are not on the critical path.
Make any allowance for the effect of interconnect capacitance.
Change the logical structure of a netlist. For example, LOON will not change a 4-OR gate to a netlist that could be faster.

The last three of these limitations are in fact requirements set for the multiplier synthesis. The outputs should all be buffered up to x2 drive strength or more, regardless of whether they are on a critical path. All inputs should be buffered to keep down their input capacitance. The timing optimisation should use 6fF of estimated wire capacitance per fanout.

The limitations can be overcome by using scripts and special synthesis flows.

drive_strength netlist instance drive
will modify a netlist by changing the drive strength of instance in netlist to the value in drive provided that its existing drive strength is less than the value requested. The script will only buffer up an instance.
make_lax netlist input_pin buffer_Prop_delay buffer_Ramp_delay buffer_pin_cap output_file loon_priority 0
will read netlist and its associated XSC file (which has netlist timing information from a previous LOON run) and create a LAX output_file with a high resistance on input_pin. The resistance value is calculated using the buffer_Prop_delay, buffer_Ramp_delay and buffer_pin_cap. The high resistance is designed (a) to put the input on the critical path; and (b) is tuned to the buffer characteristics so that a buffer is then inserted on that input (see experiment xx for more details).
The make_lax script is then inserted into the synthesis script inside a loop to buffer each instance, as in the example below acting on multi8.vst.
for bit in 7 6 5 4 3 2 1 0 do for operand in x y do ./make_lax multi8 "${operand}(${bit})" 80 15000 30 loon4xy 2 0 loon -x 0 -l loon4xy multi8 multi8_0 x2y vst vst multi8_0 multi8 done done

An estimate for interconnect capacitance can be made by using LOON with a library where the pin capacitances have been increased by the desired amount per fanout. For this experiment this is 6fF. The characterised VBE files are in directory alliance/vbe. The 0.13um characterisation VBE files in vsclib013 are copied to directory vsclib013_6 where script makecell adds 6fF to each pin capacitance, as shown in the cgi2v0x1 example below.

-- 0Ff wireload                      -- 6fF wireload
ENTITY cgi2v0x1 IS                   ENTITY cgi2v0x1 IS
GENERIC (                            GENERIC (
 ...                                  ...
  CONSTANT cin_a   : NATURAL := 8;     CONSTANT cin_a         : NATURAL := 14;
  CONSTANT cin_b   : NATURAL := 9;     CONSTANT cin_b         : NATURAL := 15;
  CONSTANT cin_c   : NATURAL := 5;     CONSTANT cin_c         : NATURAL := 11;
 ...                                  ... 
END;                                 END;

A macro is a combination of two or more library cells. The timing for macros is created in a VBE file. This allows LOON to choose the macro if its timing gives a faster critical path. Afterwards the macro is replaced with the primitive cells from which it is made. An example is the or4v5x2 macro, made from an nr3v0x1 and an nd2av0x2 cell (shown above). The timing is calculated and put into a VBE file, compared below with the regular or4v0x2 cell.

ENTITY or4v0x2 IS                               ENTITY or4v5x2 IS
GENERIC (                                       GENERIC (
  CONSTANT area          : NATURAL := 6336;       CONSTANT area          : NATURAL := 9216;
  CONSTANT cin_a         : NATURAL := 14;         CONSTANT cin_c         : NATURAL := 14;
  CONSTANT cin_b         : NATURAL := 14;         CONSTANT cin_a         : NATURAL := 15;
  CONSTANT cin_c         : NATURAL := 13;         CONSTANT cin_b         : NATURAL := 15;
  CONSTANT cin_d         : NATURAL := 13;         CONSTANT cin_d         : NATURAL := 10;
  CONSTANT rdown_a_z     : NATURAL := 1700;       CONSTANT rdown_a_z     : NATURAL := 1940;
  CONSTANT rdown_b_z     : NATURAL := 1700;       CONSTANT rdown_b_z     : NATURAL := 1940;
  CONSTANT rdown_c_z     : NATURAL := 1700;       CONSTANT rdown_c_z     : NATURAL := 1940;
  CONSTANT rdown_d_z     : NATURAL := 1700;       CONSTANT rdown_d_z     : NATURAL := 1940;
  CONSTANT rup_a_z       : NATURAL := 2150;       CONSTANT rup_a_z       : NATURAL := 2470;
  CONSTANT rup_b_z       : NATURAL := 2140;       CONSTANT rup_b_z       : NATURAL := 2470;
  CONSTANT rup_c_z       : NATURAL := 2120;       CONSTANT rup_c_z       : NATURAL := 2470;
  CONSTANT rup_d_z       : NATURAL := 2120;       CONSTANT rup_d_z       : NATURAL := 2470;
  CONSTANT tpll_a_z      : NATURAL := 188;        CONSTANT tphh_a_z      : NATURAL := 155;
  CONSTANT tphh_b_z      : NATURAL := 147;        CONSTANT tphh_b_z      : NATURAL := 147;
  CONSTANT tphh_c_z      : NATURAL := 128;        CONSTANT tphh_c_z      : NATURAL := 130;
  CONSTANT tphh_d_z      : NATURAL := 102;        CONSTANT tphh_d_z      : NATURAL := 79;
  CONSTANT tphh_a_z      : NATURAL := 161;        CONSTANT tpll_a_z      : NATURAL := 141;
  CONSTANT tpll_b_z      : NATURAL := 177;        CONSTANT tpll_b_z      : NATURAL := 130;
  CONSTANT tpll_c_z      : NATURAL := 156;        CONSTANT tpll_c_z      : NATURAL := 109;
  CONSTANT tpll_d_z      : NATURAL := 121;        CONSTANT tpll_d_z      : NATURAL := 84;
  CONSTANT transistors   : NATURAL := 14          CONSTANT transistors   : NATURAL := 15
);                                              );
PORT (                                          PORT (
  a      : in  BIT;                               a      : in  BIT;
  b      : in  BIT;                               b      : in  BIT;
  c      : in  BIT;                               c      : in  BIT;
  d      : in  BIT;                               d      : in  BIT;
  z      : out BIT;                               z      : out BIT;
  vdd    : in  BIT;                               vdd    : in  BIT;
  vss    : in  BIT                                vss    : in  BIT
);                                              );
END or4v0x2;                                    END or4v5x2;

ARCHITECTURE behaviour_data_flow OF or4v0x2 IS  ARCHITECTURE behaviour_data_flow OF or4v5x2 IS

BEGIN                                           BEGIN
  ASSERT ((vdd and not (vss)) = '1')              ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on or4v0x2"     REPORT "power supply is missing on or4v5x2"
  SEVERITY WARNING;                               SEVERITY WARNING;
  z <= (((a or b) or c) or d) after 1200 ps;      z <= (((a or b) or c) or d) after 1200 ps;
END;                                            END;

The or4v5x2 is bigger and faster than the or4v0x2, especially on pin d. By coding its timing as a VBE file in the library used by LOON, a netlist of a nr3v0x1 and nd2av0x2 can be substituted for the or4v0x2.

 $ MBK_TARGET_LIB=../vsclib013_0
 $ loon -x 0 -l loon4 multi8 multi8_0
 $ MBK_TARGET_LIB=../vsclib013_6
 $ loon -x 0 -l loon1 multi8_0 multi8
 $ MBK_TARGET_LIB=../vsclib013_0
 $ loon -x 0 -l loon0 multi8 multi8_0
 $ MBK_TARGET_LIB=../vsclib013_6
 $ loon -x 0 -l loon4 multi8_0 multi8

A LOON synthesis script is a sequence of LOON commands alternately using the 0fF and 6fF wireload libraries, and using whichever priority seems to give the best results. This sequence is continued until the critical path reaches its minimum value.

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