Characteristics of a Critical Path

In practice however gates have parasitic capacitance. In the experiments here, there is also an additional 6fF of estimated wire capacitance. In this case a larger gate is faster because the mainly fixed parasitic capacitance has less effect. So we expect the critical paths to be composed of the largest drive strengths available for each function.

The gates driving non-critical outputs, or in parallel to the ones on the critical path, should be as small as possible in order to present the smallest load to those on the critical path.

It can happen that two parallel paths have very similar delays. One is the real critical path and uses large gates. The other uses small gates and is only a critical path because the large gates have improved the speed of the first one. In this case, one can find that the critical path uses small gates, but this is only because increasing their size will slow down the first path and make it the slowest.

The critical path will be made up of large drive strength gates. If for a particular function there is only a weak drive strength, then the gates around it will also be weak and the whole critical path will be slowed down. It is important then that the library has high drive strengths for each function. If these don't exist, then the synthesis tool must use an equivalent macro netlist. With Alliance LOON, the timing of this macro must be coded into a VBE file in order for it to be recognised and selected if it is faster.

So the larger the gates, the faster they will go. There are two limits to this. One is electro-migration, a phenomenon which moves the metal in interconnect when large currents flow through it. For reliability reasons, there is a maximum current in a wire, and as a consequence the maximum drive strength of a gate. For the vsclib, this limit has been set to an x12 drive strength.

The other limit is the maximum desired physical size of the cells. The estimated wire capacitance is assumed to be constant, but in reality its value depends on the average length of a wire. If the cells are very large, the wire is longer and the estimated wire capacitance has to be higher. At this point, larger cells are not necessarily faster. Large cells also generate more noise, which could require bigger power supplies, further reducing the layout density. In order to avoid this kind of gigantism, the width of the largest drive strength for any function has been limited to 20-25 tracks, or around 7-8 gates.