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Start with Basic Inverting Gates + XOR Functions- iv1, nd2, nd3, nd4, nr2, nr3, nr4, xnr2, xor2

   
gate count               1561
number of cells           923
number of library cells     9
number of used cells        8
max fanin                  13
max input capacitance     149
max internal fanout        40
critical path  0fF       2911
critical path  6fF       4279
 

The library creation exercise starts with the basic inverting 1, 2, 3 and 4-input inverting gates plus the 2-input XOR and XNOR gates. Gates with more than four inputs are rejected because (a) they can cause routing congestion, and (b) we choose to limit the number of series connected transistors to four.

There is one drive strength per gate which uses the largest transistor sizes for the function before any folding. For the BOOG synthesis, macros have been made as described below. The actual cell usage is: 

iv1v0x2   132
nd2v0x2   226
nd3v0x1    21
nr2v0x1   262
nr3v0x05   10
nr4v1x05    2
xnr2v0x1   16
xor2v0x1  252

The cell not chosen by BOOG is the nd4v0x1.

The next step will be to add in the basic AND and OR gates.

Table of synthesis results  
  critical path (ps) gate count cell count porosity library cells used cells
synthesis 1 4279 1561 923 43%  9  8 basic inverters, NAND & NOR gates

In order to achieve this performance with Alliance synthesis, the following functions were coded as netlists. If these macros are not used, the netlist critical path deteriorates to 5371 and the area increases to 1761 gates.

an2 an2 schematic
an4 an4 schematic
aon21 aon21 schematic
cgn2 cgn2 schematic
or2 or2 schematic
or3 or3 schematic
xaon21 xaon21 schematic
xooi21 xooi21 schematic
xoon21 xoon21 schematic
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