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The critical path is the path with the biggest delay from any input to any output. The delay includes the RC delay of the input assuming an input drive strength of 1ps/fF (roughly x3 drive strength) and the delay driving a 50fF load. Each cell's delay is the average of its rise and fall delay, and the total path is the sum of these averages.
The faster the critical path the better the netlist.
The gate count is is the area occupied by the netlist.
One gate is 3 routing tracks wide, and the cell height
is 9 tracks tall. Each track is 8λ where for
this 0.13µm technology lambda = 0.055µm.
Thus the area in microns2 is
area in gates × 3 × 9 × 8 × 8 × 0.0552.
One gate occupies 5.2272µm2.
The smaller the gate count the better the netlist.
The smaller the cell count the better the netlist
1 - number_of_connectors/width_of_all_cells
where the cell width is measured in tracks.
The higher the porosity, the more routable the netlist.