2. Overview of CMOS timing models

Initial circuit Timing overview Best stage effort Library mapping Gate retiming Input buffering Better accuracy Prior art Summary Conclusions

Prop-Ramp model

The simple delay model for CMOS logic is a so-called Prop-Ramp model. The delay is:

d = Prop +Ramp × COUT

The Prop delay is the intrinsic delay with no load. The load COUT increases the delay by the value of Ramp. Consistent units here are delay measured in ps; capacitance in fF and Ramp in kΩ. In the experiments here, the delay is the average of rise and fall delays. The delay is also not modified by input slopes, but in a more sophisticated system both factors would be included.

Expressions for logical effort

For single stage inverting functions, the theory of Logical Effort shows that the delay of the function is the sum of the parasitic delay and the effort:

d = τ × (p+gh)

p is the parasitic delay of the function
g is the logical effort
h is the electrical effort which equals COUT /CIN
τ is the technology time constant, defined as the average drive resistance of an inverter multiplied by its input capacitance. For the vsclib in 0.13um, τ = 9.7ps.

By comparing both expressions for delay, we can see that
Prop = τ × p
Ramp = τ × g ×COUT /CIN

The term COUT /CIN is also called the gain or electrical effort. For a single stage it is represented by the symbol h. For a path, the symbol H is used.

The logical effort of a gate is represented by g, and for a path by G. G is the product of each gate's logical effort, or
G = Πgi

The term gh, the product of the logical effort and the electrical effort, is referred to as the stage effort f.