nr2 standard cell family
2-I/P NOR gate
The P/N ratio is kept approx equal to 2 for the nr2v0 cells and to 1.1 for the nr2v1x05 and nr2v1x1. The ratio of 2 has a good output skew, while the ratio of 1.1 is close to the fastest. The P/N ratio of 2 cannot be implemented for the x05 cell because when the series P-transistors are 16 lambda wide, the required N-transistor would be have to be 4.3 lambda, smaller than 6 lambda, which is the minimum transistor width used in the library.
z:(a+b)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nr2v1x05
30
1.65
0.36
5.2
3.4f
52
7.27
35
2.96
nr2v0x1
32
1.76
0.51
7.2
4.9f
45
4.15
43
2.87
nr2v1x1
32
1.76
0.65
8.4
5.7f
49
4.16
34
1.68
nr2v0x2
44
2.42
0.97
12.0
8.6f
41
2.15
40
1.53
nr2v0x4
62
3.41
1.50
19.8
13.7f
42
1.38
41
1.00
nr2v0x5
78
4.29
1.99
25.6
18.1f
41
1.04
41
0.76
nr2v0x7
112
6.16
2.98
38.7
27.4f
42
0.69
41
0.51
nr2v1x05
nr2v0x1
nr2v1x1
nr2v0x2
nr2v0x4
nr2v0x5
nr2v0x7