Viewable GIF files for the vsclib. This release contains 120 basic inverting and non-inverting gates. Each cell has a typical timing arc and input pin capacitance in 0.13µm generic technology, along with its leakage and dynamic power, size, layout, and the transistor schematic. Transistor sizes are given in lambda, where for this 0.13µm technology, lambda=0.055µm. The cell height is 72 lambda (3.96µm) with power supply rails 8 lambda (0.44µm) wide. The maximum P and N transistor widths are 28 lambda and 20 lambda.

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vsclib standard cell physical layout description
complete listing of 120 cells
description of the vsclib characterisation methodology

an2 standard cell family, vsclib   9× 2-AND gates
an3 standard cell family, vsclib   5× 3-AND gates
an4 standard cell family, vsclib   4× 4-AND gates
aoi21 standard cell family, vsclib   3× 2/1 AND-NOR gates
aoi22 standard cell family, vsclib   3× 2/2 AND-NOR gates
aoi31 standard cell family, vsclib   2× 3/1 AND-NOR gates
bf1 & dly standard cell family, vsclib   14× non-inverting buffers and delay cells
cgi2 standard cell family, vsclib   2× carry generator inverting gates
iv1 standard cell family, vsclib   13× inverters
mxi2 standard cell family, vsclib   3× 2-way inverting muxes
nd2 standard cell family, vsclib   6× 2-NAND gates
nd3 standard cell family, vsclib   5× 3-NAND gates
nd4 standard cell family, vsclib   4× 4-NAND gates
nd2ab standard cell family, vsclib   3× 2-OR gates (faster and larger version using inverters and 2-NAND)
nr2 standard cell family, vsclib   7× 2-NOR gates
nr3 standard cell family, vsclib   4× 3-NOR gates
nr4 standard cell family, vsclib   3× 4-NOR gates
oai21 standard cell family, vsclib   3× 2/1 OR-NAND gates
oai211 standard cell family, vsclib   2× 2/1/1 OR-NAND gates
oai22 standard cell family, vsclib   3× 2/2 OR-NAND gates
or2 standard cell family, vsclib   5× 2-OR gates
or3 standard cell family, vsclib   5× 3-OR gates
or4 standard cell family, vsclib   4× 4-OR gates
xnr2 standard cell family, vsclib   2× 2 input exclusive NOR gates
xor2 standard cell family, vsclib   6× 2 input exclusive OR gates