nr3 standard cell family
3-I/P NOR gate
Single stage 3-I/P NOR gates. The v0 gates have a P:N transistor ratio of about 2, although the nr3v0x05 N-transistor is slightly larger because of the minimum 6 lambda channel width. The nr3v1x05 has transistors close to the fastest, although with significant output skew.
z:(a+b+c)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nr3v0x05
40
2.20
0.53
7.2
4.5f
52
6.25
49
3.87
nr3v1x05
40
2.20
0.67
8.3
5.0f
57
6.25
39
2.39
nr3v0x1
58
3.19
0.99
12.8
8.5f
46
3.12
49
2.33
nr3v0x2
84
4.62
1.46
19.2
13.3f
47
2.16
50
1.54
nr3v0x05
nr3v1x05
nr3v0x1
nr3v0x2