3 cells with different drive strengths, each with a P/N ratio of about 2. The width of the P-transistor connected to pin b is designed to have a similar conductivity to the two series P-transistors, so that the output drive capability is consistent.

z:((a1+a2)*b)'

cell width

power

Generic 0.13um typical timing (ps & ps/fF), pin a2.

leakage

dynamic

tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)

lambda

0.13um

nW

nW/MHz

PinCap

PropR

RampR

PropF

RampF

oai21v0x05

40

2.20

0.34

5.0

3.3f

64

7.30

48

5.31

oai21v0x1

40

2.20

0.61

8.0

5.1f

61

4.31

45

3.09

oai21v0x2

58

3.19

1.29

15.9

9.1f

60

2.16

48

1.54

oai21v0x05

oai21v0x1

oai21v0x2