|vlsitechnology.org /wsclib /description|
wsclib standard cell library description
The wsclib is a design rule independent standard cell library which has been drawn with the Alliance Graal editor. The Alliance system allows cells drawn with Graal to be converted to CIF and GDS formats in different technologies by the use of appropriate RDS technology files. The library release tar file has examples of this layout converted into 0.13um generic technology.
The wsclib is a 80 lambda tall library with 6 internal metal tracks on an 8 lambda pitch. The maximum P transistor width is 28 lambda (including available space under the vdd), and the maximum N transistor width is 20 lambda. The layout is the same as the vsclib, but with substrate and well contacts placed top and bottom and shared with the cells in the adjacent rows.
The design rule independence is achieved by the use of lambda rules. The rule set used is similar to the one proposed by MOSIS, but relaxes some spacings and is more suitable for deep submicron technologies. A comparison of the basic rules is given on the rules page. The cells can be used with others designed to the MOSIS rules, or on their own when typically a more aggressive lambda scaling factor is possible. For generic 0.13um rules, the SCMOS DEEP rules from MOSIS would need a lambda value of 0.065um instead of the value of 0.055um which is used with the wsclib, and maybe even 0.07um (the poly overlap of gate at 2.5 lambda is very short and is the limiting feature; the wsclib rules have a 4 lambda poly overlap of gate).
In Graal, the basic design rules for wires, contacts and transistors are encoded into the RDS file. If a cell is loaded into Graal with the wrong RDS file, then the layout is unintelligible. The wsclib must be loaded with one of the vsc RDS files: vsc200.rds for data entry and viewing with the conventional lambda rules; vsc013.rds for viewing the results of scaling to generic 0.13um technology and conversion to CIF or GDS files. Other technology files will be provided in the future.
The vsclib space allocation is shown in the drawing above right. The format is a minimum height library designed for use in layout with metal-2 running vertically or horizontally. Note that you need to compile a special version of OCP and NERO for this library … see the Alliance archives for details.
The metal pitch of 8 lambda will normally give a routing pitch slightly above the minimum values allowed by a technology. The table below shows typical lambda values for different technolgies, the micron pitch of the wsclib, and the metal pitch you could expect to find at that technology node.
|Techno (um)||lambda||routing pitch||typical min pitch|
|0.25||0.125||1.00 um||0.98 um|
|0.18||0.080||0.64 um||0.58 um|
|0.13||0.055||0.44 um||0.41 um|
|0.09||0.040||0.32 um||0.30 um|
Wherever possible, the cell connectors are designed so that for a single pin they cover two or more horizontal and two or more vertical routing tracks. For any two pins, they cover three or more horizontal and vertical routing tracks; three pins cover four tracks etc. This is shown in the table below for the nr3v1x05 cell.
|Number of tracks covered by hor and ver connectors for nr3v1x05|
|Single pin (min 2)||Double pin (min 3)||Triple pin (min 4)|
All transistors in the cells are oriented vertically. Normally the output is positioned at the left of the cell rather than the right because this ensures that the output connector can be on the first vertical routing track.
The normal P/N transistor ratio has been set to be 2, except for 3-NAND and 4-NAND gates which use ratios of 2.33 and 2.5. This isn't the fastest ratio, but offers a good compromise between speed and skew and especially simplicity. See the description on logical effort for an explanation of this choice.
The maximum P-transistor size is 28 lambda, and the maximum N-transistor size is 20 lambda, giving a ratio of 1.4 between the area allocated to P and N transistors. According to a methodology which will appear in my book, this P/N transistor area ratio should be in the range of 1.3 to 1.5.
The naming convention sets a cell's drive strength proportional to the effective width of the output P transistor. A single P transistor of 28 lambda is an x2 drive strength. For each function, one of the drive strengths fills either the P or the N transistor area, with the width of the transistors in the other area set by the P/N transistor ratio of 2. Additionally there is a half drive strength function occupying the same area, and double drive strengths are made by folding transistors.
The inverting functions are made from single stage logic. None of them use three stage logic. Three stage inverting logic is slow and only ever marginally useful, and for this reason has not been included in the library.
The gap between successive drive strengths is usually 1.5:1. A coarse step increases the likelihood that there is a mismatch between the desired gate size and the size actually available from the library. As an experiment, for a 32-bit multiplier, the x3 drive strength cells were removed, and replaced by x2 or x4 cells. The delay increase in this case was only 0.4%.
The conclusion is that a fine step between drive strengths reduces the power consumption, but only has a small effect on the maximum speed. This confirms the conclusion of the Logical Effort book by Sutherland, Sproull and Harris (on page 60).
wsclib cell architecture.
nr3v1x05 layout showing contacts covering two adjacent routing tracks both vertically and horizontally.