Design rules

The MOSIS design rule numbering system has been used to list 5 different sets of CMOS layout design rules. These are:

Layout is usually drawn in the micron rules of the target technology. When a new technology becomes available, the layout of any circuits which can be migrated needs to be adapted to the new design rule set. This can be a problem if the original layout has aggressively used all the minimum widths and spacings which are then incompatible with the rules of the new technology.

A solution made famous by Mead and Conway is to draw the layout in a nominal 2µm layout and then apply a lambda scaling factor to the desired technology. This actually involves two steps.

  1. A lambda scaling factor based on the pitch of various elements like transistors, metal, poly etc.
  2. Under or over-sizing individual layers to meet specific design rules.

Thus, for the generic 0.13µm layout rules shown here, a lambda scaling factor of 0.055 is applied which scales the poly from 2µm to 0.11µm. Then the poly is oversized by 0.005µm per side to bring its width up to 0.12µm. If the foundry requires drawn poly geometries of 0.13µm, then the oversize is set to 0.01µm per side.

I think Mead and Conway used 2µm technology as their reference because it was the leading edge technology of the time. It does have the advantage that the rules can be kept integer … that is the minimum segment length is 1λ. Other reference technologies are possible, and the Alliance sxlib uses 1µm.

The layout rules includes a generic 0.13µm set. Generic means that layout drawn with these rules could be ported to a 0.13µm foundry with no scaling, but some individual layers (especially contact, via, implant and poly) might need to be over or undersized.

The scaling factor from the pharosc rules to the 0.13µm rules is λ=0.055, and for scmos-DEEP it is λ=0.07. A factor of λ=0.055 has been used for the sxlib, although this gives design rule violations in the final layout. The ssxlib has been created to overcome this problem. The scmos rules will need a scaling factor even larger than λ=0.07 because the rule set is not well tuned to the requirements of deep submicron layout.

For some rules, the generic 0.13µm rules are more aggressive than the lambda rules scaled by 0.055. This implies that layout directly drawn in the generic 0.13µm rules could be denser. However, the risk is that this layout could not then easily be ported to other technologies.

When we talk about lambda based layout design rules, there can in fact be more than one version. The layout rules change with each new technology and the fit between the lambda and micron rules can be better or worse, and this directly affects the scaling factor which is achievable.