Selection of standard cell library densities

This page gives a table of various standard cell densities in technologies with minimum transistor lengths ranging from 0.35μm to 90nm. The libraries which have height and width values in lambda are scaled using the appropriate value of lambda. The Virage, Artisan, Virtual Silicon, TSMC and UMC densities are from their published literature (follow the links for more info). If they provide no public information which allows the numbers to be confirmed, then the density is marked as a claim. The foundry densities listed are real libraries known to the author under NDA, so their names can't be revealed.

A gate is considered to be 3 tracks wide regardless of the width of an actual 2-NAND gate. In many cases, the vsclib for example, a 2-NAND gate occupies 4 routing tracks. This means that, while the densities might look good, the number of gates in a netlist is higher than it is in the other libraries.