an4 standard cell family
4-I/P AND gate
There are two versions of these AND gates. The v0 cells have been designed for high speed, and the v4 cells for low power. For both versions, the output inverter P:N transistor ratio is 2 and the 4-NAND gate transistor ratio is 2.5, which is close to the fastest ratio. The gain between the first and second stages is high for the v0 cells giving a gate optimised for speed. The gain in the v4 cells is set to 4, more suitable for a low power option.
z:(a*b*c*d)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
an4v4x1
60
3.30
0.68
16.1
2.3f
121
3.47
141
2.76
an4v0x1
60
3.30
1.10
19.7
4.1f
94
3.38
106
2.63
an4v0x2
60
3.30
1.50
26.5
5.0f
97
2.15
106
1.66
an4v0x4
96
5.28
2.54
42.5
7.6f
94
1.08
106
0.83
an4v4x1
an4v0x1
an4v0x2
an4v0x4