The output is the inverted carry of bits a and b and carry input c, with the delay from pin c being favoured. The cells here use a P/N ratio of 2.

z:((a*b)+(a*c)+(b*c))'

cell width

power

Generic 0.13um typical timing (ps & ps/fF), pin c.

leakage

dynamic

tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)

lambda

0.13um

nW

nW/MHz

PinCap

PropR

RampR

PropF

RampF

cgi2v0x05

58

3.19

0.53

7.3

3.2f

58

7.34

54

5.32

cgi2v0x1

58

3.19

0.90

11.7

5.1f

55

4.35

51

3.10

cgi2v0x05

cgi2v0x1