This style of 2-way mux has the smallest dimensions, although not the fastest speed. For fastest speed, the output should be driven through an inverter followed by a transfer gate. However, inserting the metal wire to join the P and N transistors of the inverters makes the cell wider (connecting n2 to n4 and n1 to n3 in the schematics below, and making sure that the transistors closest to the supply are connected to s or sn). The cells here use a P/N ratio of 2. The Ramp Rise time reported below is an average of when the other data input is high and low, which is an approximation. The .LIB file has the correct timing for each case.

z:((a0*s')+(a1*s))'

cell width

power (pins a0,a1)

Generic 0.13um typical timing (ps & ps/fF), pin a0 (pin s=0).

leakage

dynamic

tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)

lambda

0.13um

nW

nW/MHz

PinCap

PropR

RampR

PropF

RampF

mxi2v0x05

56

3.08

0.72

7.9

3.4f

59

7.40

60

5.33

mxi2v0x1

60

3.30

1.06

12.1

5.3f

63

4.52

54

3.10

mxi2v0x2

112

6.16

2.13

25.1

10.9f

65

2.26

56

1.55

mxi2v0x05

mxi2v0x1

mxi2v0x2