nd2 standard cell family

2-I/P NAND gate

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nd2 symbol

Single stage 2-I/P NAND gates. 6 drive strengths with a P/N ratio of 2.

z:(a*b)'

cell width

power

Generic 0.13um typical timing (ps & ps/fF), pin b.

leakage

dynamic

tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)

lambda

0.13um

nW

nW/MHz

PinCap

PropR

RampR

PropF

RampF

nd2v0x05

28

1.54

0.27

3.4

2.1f

46

7.42

35

5.27

nd2v0x1

28

1.54

0.46

5.4

3.4f

44

4.23

34

3.07

nd2v0x2

32

1.76

0.79

9.0

5.7f

44

2.47

35

1.83

nd2v0x4

50

2.75

1.57

17.3

11.0f

43

1.23

34

0.92

nd2v0x6

70

3.85

2.36

27.0

17.2f

44

0.82

35

0.61

nd2v0x8

90

4.95

3.14

35.6

22.9f

43

0.62

35

0.46

nd2v0x05 standard cell layout

nd2v0x05 schematicnd2v0x05

nd2v0x1 standard cell layout

nd2v0x1 schematicnd2v0x1

nd2v0x2 standard cell layout

nd2v0x2 schematicnd2v0x2

nd2v0x4 standard cell layout

nd2v0x4 schematicnd2v0x4

nd2v0x6 standard cell layout

nd2v0x6 schematicnd2v0x6

nd2v0x8 standard cell layout

nd2v0x8 schematicnd2v0x8