or3 standard cell family
3-I/P OR gate
The v0 cells have been designed for high speed. The or3v4x05 has been designed with a minimum input capacitance and has a high fall Prop delay because of the small P transistors on the NOR3 gate. The output inverter P:N transistor ratio is 2 and the 3-NOR gate transistor ratio is also 2 except where the 3-NOR gate N transistors must be set to a minimum width.
z:(a+b+c)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
or3v4x05
50
2.75
0.53
13.0
2.6f
74
4.98
170
4.85
or3v0x05
50
2.75
0.67
14.5
4.0f
82
4.99
114
4.34
or3v0x1
52
2.86
0.84
18.4
4.7f
90
3.31
113
2.76
or3v0x2
70
3.85
1.17
24.3
5.9f
93
2.12
109
1.72
or3v0x4
80
4.40
2.00
38.6
8.5f
91
1.06
112
0.86
or3v4x05
or3v0x05
or3v0x1
or3v0x2
or3v0x4