xor2 standard cell family
2-I/P exclusive OR gate
There are a number of ways to implement an XOR gate, and 4 of them are shown here.
- xor2v0 has the smallest number of transistors.
- xor2v1 is the classic two inverters with transfer gate onto the output node.
- xor2v2 is an alternative inverter plus transfer gate configuration.
- xor2v7 is a 2-NAND and OR-NAND combination with output buffering inverter. The schematic came from a public web site; the layout is mine.
XOR2 gates are one of the most common gate types: in most designs they are amongst the top-10 used cells. Their speed has a direct impact
on overall circuit performance, as they are widely used in arithmetic functions. The 4 variants here have been characterised in the generic
0.13um technology, and a summary of their performance is shown below. The fastest gate is the xor2v2. The xor2v0 is also nice because it is
the smallest. The xor2v7 is fairly nasty. It's big and slow, and the transistors are wrongly sized.
z:(a^b)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
xor2v0x05, b=1
60
3.30
1.06
13.1
3.2f
82
5.01
76
4.15
xor2v0x1, b=1
64
3.52
1.74
19.3
5.0f
78
3.08
69
2.31
xor2v1x1, b=1
72
3.96
1.14
31.1
5.2f
84
3.55
72
2.99
xor2v2x1, b=1
70
3.85
1.19
17.1
4.6f
97
4.83
47
2.27
xor2v2x2, b=1
72
3.96
2.07
25.7
7.1f
90
2.74
43
1.26
xor2v7x1, b=1
80
4.40
1.18
29.2
6.4f
141
5.40
147
3.85
xor2v0x05, b=0
60
3.30
1.06
19.4
3.2f
105
7.34
109
5.37
xor2v0x1, b=0
64
3.52
1.74
29.0
5.0f
89
4.18
98
2.87
xor2v1x1, b=0
72
3.96
1.14
32.4
5.2f
94
3.48
111
2.86
xor2v2x1, b=0
70
3.85
1.19
23.3
4.6f
82
4.28
112
4.14
xor2v2x2, b=0
72
3.96
2.07
34.8
7.1f
74
2.53
100
2.31
xor2v7x1, b=0
80
4.40
1.18
19.7
6.4f
99
5.42
101
3.84
xor2v0x05
xor2v0x1
xor2v1x1
xor2v2x1
xor2v2x2
xor2v7x1